Commit message (Collapse) | Author | Age | Files | Lines | |
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* | Add BaseClusterInfo for base implementation | gatecat | 2021-05-06 | 1 | -0/+44 |
| | | | | Signed-off-by: gatecat <gatecat@ds0.me> | ||||
* | arch_api: Outline of new cluster API | gatecat | 2021-05-06 | 4 | -14/+43 |
| | | | | Signed-off-by: gatecat <gatecat@ds0.me> | ||||
* | Merge pull request #692 from davidcorrigan714/patch-1 | gatecat | 2021-05-01 | 1 | -2/+2 |
|\ | | | | | Fix variable name in bits.h for MSVC builds | ||||
| * | Update bits.h | David Corrigan | 2021-04-30 | 1 | -2/+2 |
|/ | | | Fixed the variable name for windows MSVC builds. | ||||
* | clangformat | gatecat | 2021-04-30 | 1 | -40/+30 |
| | | | | Signed-off-by: gatecat <gatecat@ds0.me> | ||||
* | Merge pull request #664 from YosysHQ/gatecat/nexus-counter | gatecat | 2021-04-30 | 8 | -3/+61 |
|\ | | | | | interchange/nexus: Add counter example | ||||
| * | interchange/nexus: Add counter example | gatecat | 2021-04-30 | 8 | -3/+61 |
|/ | | | | Signed-off-by: gatecat <gatecat@ds0.me> | ||||
* | Merge pull request #690 from YosysHQ/gatecat/interchange-wire-types | gatecat | 2021-04-30 | 5 | -4/+39 |
|\ | | | | | interchange: Add wire types | ||||
| * | interchange: Bump versions | gatecat | 2021-04-30 | 1 | -2/+2 |
| | | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me> | ||||
| * | interchange: Implement getWireType | gatecat | 2021-04-30 | 3 | -1/+20 |
| | | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me> | ||||
| * | interchange: Add wire types to chipdb | gatecat | 2021-04-30 | 1 | -1/+17 |
|/ | | | | Signed-off-by: gatecat <gatecat@ds0.me> | ||||
* | Merge pull request #689 from adamgreig/ecp5-alu | gatecat | 2021-04-29 | 3 | -1/+140 |
|\ | | | | | ECP5 ALU54B placement support | ||||
| * | Only set CIBOUT_BYP on MULTs that are not feeding an ALU. | Adam Greig | 2021-04-29 | 1 | -1/+1 |
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| * | Add check_alu to Ecp5Packer | Adam Greig | 2021-04-29 | 1 | -15/+123 |
| | | | | | | | | | | | | | | | | | | | | | | Checks that every ALU54B is correctly connected to two MULT18X18Ds: * SIGNEDIA and SIGNEDIB connected to SIGNEDP * MA and MB connected to P * A and B connected to {ROA, ROB} Diamond enforces these requirements; the connections are fixed in any event so no other connection is possible. | ||||
| * | Add relative constraints to position MULT18X18D near connected ALU54B. | Adam Greig | 2021-04-29 | 2 | -0/+29 |
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| * | Add ALU54B.REG_OPCODEOP1_1_CLK parameter support | Adam Greig | 2021-04-29 | 1 | -0/+2 |
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* | Merge pull request #685 from YosysHQ/gatecat/nexus-routing | gatecat | 2021-04-25 | 1 | -4/+1 |
|\ | | | | | nexus: Enable placeAllAtOnce | ||||
| * | nexus: Enable placeAllAtOnce | gatecat | 2021-04-25 | 1 | -4/+1 |
|/ | | | | Signed-off-by: gatecat <gatecat@ds0.me> | ||||
* | Merge pull request #683 from antmicro/interchange-allow-loc-keyword | gatecat | 2021-04-20 | 1 | -2/+4 |
|\ | | | | | interchange: allow LOC keyword in XDC files | ||||
| * | interchange: allow LOC keyword in XDC files | Jan Kowalewski | 2021-04-20 | 1 | -2/+4 |
| | | | | | | | | Signed-off-by: Jan Kowalewski <jkowalewski@antmicro.com> | ||||
* | | Merge pull request #682 from YosysHQ/gatecat/default-cellpins | gatecat | 2021-04-20 | 6 | -8/+81 |
|\ \ | | | | | | | interchange: Handle missing/disconnected cell pins | ||||
| * | | interchange: Bump versions | gatecat | 2021-04-20 | 2 | -1/+1 |
| | | | | | | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me> | ||||
| * | | interchange: Handle disconnected/missing cell pins | gatecat | 2021-04-19 | 3 | -6/+56 |
| | | | | | | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me> | ||||
| * | | interchange: Add default cell connections to chipdb | gatecat | 2021-04-19 | 1 | -1/+24 |
|/ / | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me> | ||||
* | | Merge pull request #681 from YosysHQ/gatecat/more-pybindings | gatecat | 2021-04-15 | 2 | -0/+8 |
|\ \ | | | | | | | Add Python bindings for placement tests | ||||
| * | | Add Python bindings for placement tests | gatecat | 2021-04-15 | 2 | -0/+8 |
| | | | | | | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me> | ||||
* | | | Merge pull request #680 from YosysHQ/gatecat/fix-util | gatecat | 2021-04-15 | 1 | -2/+2 |
|\ \ \ | |/ / |/| | | Fix utilisation report when bel buckets are used | ||||
| * | | Fix utilisation report when bel buckets are used | gatecat | 2021-04-15 | 1 | -2/+2 |
|/ / | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me> | ||||
* | | Merge pull request #678 from acomodi/initial-fasm-generation | gatecat | 2021-04-14 | 21 | -71/+136 |
|\ \ | | | | | | | interchange: add FASM generation target and clean-up tests | ||||
| * | | gh-actions: increase python-fpga-interchange tag version | Alessandro Comodi | 2021-04-14 | 1 | -1/+1 |
| | | | | | | | | | | | | Signed-off-by: Alessandro Comodi <acomodi@antmicro.com> | ||||
| * | | interchange: add FASM generation target and clean-up tests | Alessandro Comodi | 2021-04-14 | 20 | -70/+135 |
| |/ | | | | | | | Signed-off-by: Alessandro Comodi <acomodi@antmicro.com> | ||||
* | | Merge pull request #679 from YosysHQ/gatecat/disable-absl | gatecat | 2021-04-14 | 11 | -63/+54 |
|\ \ | |/ |/| | Hash table changes | ||||
| * | ci: Re-enable abseil for interchange CI | gatecat | 2021-04-14 | 1 | -1/+1 |
| | | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me> | ||||
| * | Hash table refactoring | gatecat | 2021-04-14 | 10 | -62/+53 |
|/ | | | | Signed-off-by: gatecat <gatecat@ds0.me> | ||||
* | Merge pull request #677 from YosysHQ/gatecat/ppip-no-input | gatecat | 2021-04-13 | 1 | -14/+35 |
|\ | | | | | interchange: Allow pseudo-cells with no input pins | ||||
| * | interchange: Allow pseudo-cells with no input pins | gatecat | 2021-04-13 | 1 | -14/+35 |
| | | | | | | | | | | | | | | These are used for the LUT-as-GND-driver pseudo-pips in the Nexus arch, which will probably be required for UltraScale too. Signed-off-by: gatecat <gatecat@ds0.me> | ||||
* | | Merge pull request #676 from YosysHQ/gatecat/fix-sta-crash | gatecat | 2021-04-13 | 2 | -58/+73 |
|\ \ | |/ |/| | timing: Fix domain init when loops are present | ||||
| * | timing: Fix domain init when loops are present | gatecat | 2021-04-13 | 2 | -58/+73 |
|/ | | | | Signed-off-by: gatecat <gatecat@ds0.me> | ||||
* | Merge pull request #674 from adamgreig/heap-spreader-fix | gatecat | 2021-04-12 | 1 | -0/+4 |
|\ | | | | | HeAP: Skip high-strength cells in both cell loops | ||||
| * | HeAP: Skip high-strength cells in both cell loops. | Adam Greig | 2021-04-12 | 1 | -0/+4 |
| | | | | | | | | | | | | Previously only the first loop skipped cells with high belStrength, but they can't be processed by the second loop either, so skip them there too. | ||||
* | | Merge pull request #673 from YosysHQ/gatecat/fix-fast-bels-ref | gatecat | 2021-04-12 | 1 | -14/+18 |
|\ \ | |/ |/| | fast_bels: Don't return pointer that might become invalid | ||||
| * | fast_bels: Don't return pointer that might become invalid | gatecat | 2021-04-12 | 1 | -14/+18 |
| | | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me> | ||||
* | | clangformat | gatecat | 2021-04-12 | 8 | -133/+134 |
|/ | | | | Signed-off-by: gatecat <gatecat@ds0.me> | ||||
* | Merge pull request #668 from YosysHQ/gatecat/cell-bel-name-vcc | gatecat | 2021-04-09 | 1 | -6/+10 |
|\ | | | | | interchange: Disambiguate cell and bel pins when creating Vcc ties | ||||
| * | interchange: Disambiguate cell and bel pins when creating Vcc ties | gatecat | 2021-04-09 | 1 | -6/+10 |
| | | | | | | | | | | | | | | | | | | | | | | | | The pins created for tieing to Vcc were being named after the bel pin, relying on the fact that Xilinx names cell and bel pins differently for LUTs. This isn't true for Nexus devices which uses the same names for both, and was causing a failure as a result. This uses a "PHYS_" prefix that's highly unlikely to appear in a cell pin name to disambiguate. Signed-off-by: gatecat <gatecat@ds0.me> | ||||
* | | Merge pull request #669 from YosysHQ/gatecat/prjoxide-pin | gatecat | 2021-04-09 | 2 | -0/+3 |
|\ \ | |/ |/| | interchange: Pin prjoxide commit in CI | ||||
| * | interchange: Pin prjoxide commit | gatecat | 2021-04-09 | 2 | -0/+3 |
|/ | | | | Signed-off-by: gatecat <gatecat@ds0.me> | ||||
* | Merge pull request #667 from YosysHQ/fix_qt | Miodrag Milanović | 2021-04-08 | 1 | -0/+4 |
|\ | | | | | Add same fix as in issue #373 | ||||
| * | Add same fix as in issue #373 | Miodrag Milanovic | 2021-04-08 | 1 | -0/+4 |
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* | Merge pull request #665 from cr1901/optional-lto | gatecat | 2021-04-07 | 1 | -2/+13 |
|\ | | | | | Add CMake option to enable IPO (enabled by default). |