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Signed-off-by: gatecat <gatecat@ds0.me>
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Fix global normalisation for LIFCL-17
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Signed-off-by: gatecat <gatecat@ds0.me>
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Signed-off-by: gatecat <gatecat@ds0.me>
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Add counter test for FPGA interchange
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Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
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Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
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Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
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Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
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Add placement sanity check in placer_heap.
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Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
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Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
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Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
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Also check return of placer1_refine.
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
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Gowin DFF fixes
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Prevent trival misplacements in placer1.
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Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
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Remove unused advanced timing constraint API
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This API was simply an attractive nuisance as no code was ever developed
to actually process timing constraints (other than clock constraints
which use a different API).
While I do want to consider basic false path support, among other
things, in the near future; I plan for this to use a new API that
doesn't add complexity to the BaseCtx/Context monstrosity and that is
easier to use on the timing analysis side.
Signed-off-by: gatecat <gatecat@ds0.me>
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Allow router2 to use routed but not fixed arcs.
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Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
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cmake: Don't enable any -Werror flags without opt-in
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Tighten up compiler flags
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Signed-off-by: gatecat <gatecat@ds0.me>
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-Werror is not enabled by default, except on CI and for a few specific common traps, to avoid the inevitable breakages when new compiler versions add new diagnostics.
Signed-off-by: gatecat <gatecat@ds0.me>
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Add constant network support to FPGA interchange arch
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Fixes:
- Only use map constant pins during routing, and not during placement.
- Unmapped cell ports have no BEL pins.
- Fix SiteRouter congestion not taking into account initial expansion.
- Fix psuedo-site pip output.
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
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Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
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Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
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Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
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Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
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Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
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Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
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Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
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Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
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Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
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Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
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Also add debug_test target to debug archcheck.
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
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Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
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Add dynamic bitarray to common library.
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Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
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Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
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Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
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Signed-off-by: gatecat <gatecat@ds0.me>
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Change CellInfo in getBelPinsForCellPin to be const.
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Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
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Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
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Run "make clangformat" to fix formatting in new Bits library.
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