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* nexus: Add timing data for LRAMgatecat2022-08-103-0/+30
* Merge pull request #1010 from YosysHQ/gatecat/idfmyrtle2022-08-1022-153/+152
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| * refactor: id(stringf(...)) to new idf(...) helpergatecat2022-08-1022-153/+152
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* Merge pull request #1008 from YosysHQ/gatecat/generic-addbelpinmyrtle2022-08-043-25/+12
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| * generic: addBelPin with direction as an arggatecat2022-08-043-25/+12
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* Merge pull request #1004 from yrabbit/fix-muxesmyrtle2022-07-217-38/+26
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| * Merge branch 'master' into fix-muxesYRabbit2022-07-201-1/+1
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* | Merge pull request #1005 from YosysHQ/gatecat/nexus-ram-fixesmyrtle2022-07-191-1/+1
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| * | nexus: Fix CSDECODE parsinggatecat2022-07-191-1/+1
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| * gowin: fix compilationYRabbit2022-07-191-8/+0
| * gowin: Remove incomprehensible names of the muxesYRabbit2022-07-197-34/+30
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* Merge pull request #998 from yrabbit/clock-wipmyrtle2022-07-186-1/+479
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| * Merge branch 'master' into clock-wipYRabbit2022-07-1016-49/+198
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* | Merge pull request #999 from YosysHQ/gatecat/pseudocell-apimyrtle2022-07-0816-49/+198
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| * | netlist: Add PseudoCell APIgatecat2022-07-0816-49/+198
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| * gowin: Remove unnecessary functionsYRabbit2022-07-052-33/+9
| * Merge branch 'master' into clock-wipYRabbit2022-07-059-106/+211
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* | Merge pull request #995 from pepijndevos/shadowrammyrtle2022-07-056-0/+187
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| * | use DFF RAM modePepijn de Vos2022-07-021-1/+4
| * | Merge branch 'master' into shadowramPepijn de Vos2022-07-029-25/+324
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| * | | hook up CE maybePepijn de Vos2022-06-163-0/+4
| * | | lutram actually PnRsPepijn de Vos2022-06-065-38/+43
| * | | WIP shadowramPepijn de Vos2022-06-056-0/+175
* | | | Merge pull request #1001 from YosysHQ/gatecat/generic-shared-pybmyrtle2022-07-052-105/+18
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| * | | | generic: Use arch_pybindings_sharedgatecat2022-07-042-105/+18
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* | | | Merge pull request #1002 from gsomlo/gls-pybind11-unbundlemyrtle2022-07-051-1/+6
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| * | | Enable building against unbundled pybind11Gabriel Somlo2022-07-041-1/+6
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| | * gowin: fix compilationYRabbit2022-07-041-0/+1
| | * gowin: Let the placer know about global networksYRabbit2022-07-045-259/+367
| | * Merge branch 'master' into clock-wipYRabbit2022-07-042-10/+11
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* | | Merge pull request #1000 from YosysHQ/gatecat/fix-empty-portsmyrtle2022-06-261-9/+9
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| * | | ice40: Fix accidental creation of empty portsgatecat2022-06-251-9/+9
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* | | Merge pull request #997 from Chandler-Kluser/mastermyrtle2022-06-231-1/+2
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| * | | Update README.mdChandler Klüser2022-06-221-1/+2
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| | * gowin: process the CLK ports of the ODDR[C] primitivesYRabbit2022-06-242-7/+9
| | * gowin: add a separate router for the clocksYRabbit2022-06-235-1/+392
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* | Disable broken and failing interchange CIgatecat2022-06-211-0/+0
* | clangformatgatecat2022-06-121-1/+1
* | ecp5: Bind write_bitstream to Pythongatecat2022-06-091-0/+3
* | Merge pull request #996 from yrabbit/snmyrtle2022-06-091-7/+11
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| * | gowin: Use local aliasesYRabbit2022-06-091-7/+11
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* | Merge pull request #993 from yrabbit/lw-wip-1myrtle2022-06-075-8/+299
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| * gowin: Add support for long wiresYRabbit2022-05-275-8/+299
* | Merge pull request #992 from antmicro/mdudek/nexus_write_dccmyrtle2022-05-271-3/+2
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| * | Change write_dcc to work with tilegroups from prjoxideMaciej Dudek2022-05-271-3/+2
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* | Merge pull request #990 from YosysHQ/gatecat/fix-988myrtle2022-05-221-5/+0
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| * | Don't assert on mixed domain paths in reportgatecat2022-05-221-5/+0
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* | Merge pull request #989 from YosysHQ/lofty/cmake-bumpmyrtle2022-05-211-1/+1
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| * Bump minimum CMake to 3.13Lofty2022-05-211-1/+1
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* Merge pull request #985 from antmicro/interchange-lut-constantsmyrtle2022-05-135-58/+180
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