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Author
Age
Files
Lines
*
router2: Add heatmap by routing resource type
gatecat
2021-05-20
3
-3
/
+49
*
Run clangformat
gatecat
2021-05-16
1
-1
/
+1
*
mistral: Tidying up
gatecat
2021-05-15
2
-2
/
+3
*
router2: Hacky workaround for slow Cyclone V convergence
gatecat
2021-05-15
1
-3
/
+3
*
router2: Reduce verbosity when debugging
gatecat
2021-05-15
1
-0
/
+2
*
mistral: Add stub pack/place/route functions
gatecat
2021-05-15
1
-1
/
+1
*
archcheck: Use old connectivity check for CycloneV
gatecat
2021-05-15
1
-1
/
+29
*
cyclonev: Add names and archcheck fixes
gatecat
2021-05-15
2
-0
/
+22
*
router2: Add some boundness statistics
gatecat
2021-05-12
1
-0
/
+33
*
router2: Fix a typo
gatecat
2021-05-11
1
-1
/
+1
*
command: Allow debug output for just placer or router
gatecat
2021-05-11
1
-0
/
+11
*
router2: Reserve wires in more complex cases
gatecat
2021-05-06
1
-13
/
+39
*
router2: Dynamicly expand bounding box based on congestion
gatecat
2021-05-06
1
-10
/
+22
*
Add stub cluster API impl for remaining arches
gatecat
2021-05-06
1
-0
/
+2
*
base_arch: Fix typo in getClusterPlacement
gatecat
2021-05-06
1
-1
/
+1
*
Update placers to use new cluster APIs
gatecat
2021-05-06
9
-344
/
+149
*
Add default base implementation of cluster API
gatecat
2021-05-06
3
-5
/
+97
*
Add BaseClusterInfo for base implementation
gatecat
2021-05-06
1
-0
/
+44
*
arch_api: Outline of new cluster API
gatecat
2021-05-06
2
-9
/
+9
*
Update bits.h
David Corrigan
2021-04-30
1
-2
/
+2
*
interchange: Implement getWireType
gatecat
2021-04-30
1
-0
/
+2
*
Merge pull request #681 from YosysHQ/gatecat/more-pybindings
gatecat
2021-04-15
1
-0
/
+3
|
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*
Add Python bindings for placement tests
gatecat
2021-04-15
1
-0
/
+3
*
|
Fix utilisation report when bel buckets are used
gatecat
2021-04-15
1
-2
/
+2
|
/
*
Hash table refactoring
gatecat
2021-04-14
2
-50
/
+28
*
timing: Fix domain init when loops are present
gatecat
2021-04-13
2
-58
/
+73
*
Merge pull request #674 from adamgreig/heap-spreader-fix
gatecat
2021-04-12
1
-0
/
+4
|
\
|
*
HeAP: Skip high-strength cells in both cell loops.
Adam Greig
2021-04-12
1
-0
/
+4
*
|
fast_bels: Don't return pointer that might become invalid
gatecat
2021-04-12
1
-14
/
+18
|
/
*
Fix bug in router2 where router may give up too early.
Keith Rothman
2021-04-06
1
-1
/
+13
*
interchange: Fix illegal placements
gatecat
2021-03-30
1
-1
/
+3
*
Add initial handling of local site inverters and constant signals.
Keith Rothman
2021-03-25
1
-2
/
+3
*
Use new parameter definition data in FPGA interchange processing.
Keith Rothman
2021-03-23
2
-1
/
+130
*
Merge pull request #634 from litghost/add_get_bel_pin_type
gatecat
2021-03-22
1
-0
/
+2
|
\
|
*
Add getBelPinType to Python interface.
Keith Rothman
2021-03-22
1
-0
/
+2
*
|
Add "checkPipAvailForNet" to Arch API.
Keith Rothman
2021-03-22
3
-13
/
+13
|
/
*
Refactor header structures in FPGA interchange Arch.
Keith Rothman
2021-03-19
1
-0
/
+3
*
Run "make clangformat". to fix up master.
Keith Rothman
2021-03-18
4
-4
/
+3
*
Moving hash map/set type selection to header.
Keith Rothman
2021-03-17
2
-8
/
+52
*
Add missing includes to fix WASI build.
whitequark
2021-03-16
2
-0
/
+5
*
Use NEXTPNR_NAMESPACE macro's now that headers are seperated.
Keith Rothman
2021-03-15
9
-23
/
+29
*
Merge pull request #621 from litghost/fix_header_nightmare
gatecat
2021-03-15
30
-2395
/
+3104
|
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|
*
Split nextpnr.h to allow for linear inclusion.
Keith Rothman
2021-03-15
30
-2395
/
+3104
*
|
opt-timing: Skip undriven nets
gatecat
2021-03-15
1
-0
/
+2
|
/
*
Add support for partially routed nets from the placer in router2.
Keith Rothman
2021-03-12
2
-28
/
+54
*
Add diagnostic prints to debug lookahead performance.
Keith Rothman
2021-03-10
1
-13
/
+41
*
Only depend on Abseil in threaded builds.
whitequark
2021-03-10
1
-0
/
+6
*
Merge pull request #607 from litghost/add_absl_flat_hash_map
gatecat
2021-03-09
1
-1
/
+2
|
\
|
*
Add absl::flat_hash_map.
Keith Rothman
2021-03-01
1
-1
/
+2
*
|
Merge pull request #609 from YosysHQ/gatecat/sta-v2
gatecat
2021-03-09
8
-242
/
+937
|
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