aboutsummaryrefslogtreecommitdiffstats
path: root/ecp5/arch.cc
Commit message (Expand)AuthorAgeFilesLines
* Fix clangformat and execute itMiodrag Milanovic2020-06-271-12/+8
* Simplify and improve chipdb embedding/loading.whitequark2020-06-261-49/+33
* CMake: rewrite chipdb handling from ground up.whitequark2020-06-251-2/+2
* Port nextpnr-{ice40,ecp5} to WASI.whitequark2020-05-231-2/+3
* ecp5: MULT18X18D timing fixesDavid Shah2020-05-011-10/+26
* No cell delay for clocked MULT18X18DRoss Schlaikjer2020-04-301-0/+2
* Issue warning for mixed-mode inputsRoss Schlaikjer2020-04-291-24/+11
* Handle register timing caseRoss Schlaikjer2020-04-291-6/+58
* Use registered port class on mult18x18Ross Schlaikjer2020-04-291-3/+5
* Alter MULT18X18D timing db based on register configRoss Schlaikjer2020-04-281-1/+1
* Merge pull request #423 from rschlaikjer/rschlaikjer-regmode-timing-databaseDavid Shah2020-04-071-4/+2
|\
| * Actually just move all the logic to ArchInfoRoss Schlaikjer2020-04-071-15/+2
| * Extract regmode configuration to ArchInfoRoss Schlaikjer2020-04-071-8/+4
| * Change timing database lookup based on REGMODE valueRoss Schlaikjer2020-04-071-4/+19
* | ecp5: Proper support for '12k' deviceDavid Shah2020-03-131-2/+7
|/
* router2: Improve flow and log outputDavid Shah2020-02-031-1/+1
* Allow selection of router algorithmDavid Shah2020-02-031-2/+16
* router2: Make magic numbers configurableDavid Shah2020-02-031-1/+1
* ecp5: Improve bounding box accuracyDavid Shah2020-02-031-4/+19
* ecp5: router2 main renameDavid Shah2020-02-031-1/+1
* ecp5: Router2 test integrationDavid Shah2020-02-031-1/+38
* Merge remote-tracking branch 'origin/master' into mmicko/ecp5_guiMiodrag Milanovic2019-12-281-1/+11
|\
| * ecp5: Add an error for out-of-sync constids and bbaDavid Shah2019-10-261-0/+3
| * ecp5: Fix routing to shared DSP control inputsDavid Shah2019-10-251-1/+8
* | move bel creation to gfx.ccMiodrag Milanovic2019-12-151-122/+2
* | fix formatingMiodrag Milanovic2019-12-141-2/+1
* | more new wires addedMiodrag Milanovic2019-12-141-1/+10
* | ebr, mult and alu nice displayMiodrag Milanovic2019-12-141-1/+1
* | clangformat runMiodrag Milanovic2019-12-081-27/+30
* | display IOs properlyMiodrag Milanovic2019-12-071-21/+5
* | More bels show properlyMiodrag Milanovic2019-12-071-43/+82
* | add dcca bels and dummy parts for other belsMiodrag Milanovic2019-12-071-9/+54
* | more pips, and valid mappingMiodrag Milanovic2019-11-101-4/+4
* | Draw some pips, fixed H6 and V6Miodrag Milanovic2019-11-091-1/+22
* | Show V02/V06/H02/H06Miodrag Milanovic2019-10-251-1/+1
* | Split graphics calls for wires into gfx.ccMiodrag Milanovic2019-10-201-268/+3
* | muxes only together with slicesMiodrag Milanovic2019-10-201-9/+7
* | Remove not used lineMiodrag Milanovic2019-10-201-2/+0
* | Simplify layout of elementsMiodrag Milanovic2019-10-201-170/+114
* | fix slice wireMiodrag Milanovic2019-10-201-20/+20
* | bound signalsMiodrag Milanovic2019-10-201-0/+65
* | more wires between switchboxesMiodrag Milanovic2019-10-201-1/+37
* | Add more types of wiresMiodrag Milanovic2019-10-201-176/+191
* | finixed slice wiresMiodrag Milanovic2019-10-201-0/+27
* | wd wiresMiodrag Milanovic2019-10-201-1/+21
* | Fix look of some wiresMiodrag Milanovic2019-10-201-6/+9
* | Add output wiresMiodrag Milanovic2019-10-201-0/+35
* | fix mux displayMiodrag Milanovic2019-10-201-2/+2
* | set wire active flagMiodrag Milanovic2019-10-201-1/+1
* | clk and lsr muxesMiodrag Milanovic2019-10-201-1/+62
generated by cgit v1.2.3 (git 2.25.1) at 2024-07-01 03:15:50 +0000