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* refactor: Use constids instead of id("..")gatecat2022-02-161-19/+18
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* archapi: Use arbitrary rather than actual placement in predictDelaygatecat2021-12-191-13/+8
| | | | | | | | | | | | This makes predictDelay be based on an arbitrary belpin pair rather than a arc of a net based on cell placement. This way 'what-if' decisions can be evaluated without actually changing placement; potentially useful for parallel placement. A new helper predictArcDelay behaves like the old predictDelay to minimise the impact on existing passes; only arches need be updated. Signed-off-by: gatecat <gatecat@ds0.me>
* ecp5: LUT permutation supportgatecat2021-12-131-0/+4
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* ecp5: Use a vector rather than dictMatt Johnston2021-12-121-0/+21
| | | | | This improves router1 performance vs the default dict Using it for wire2net, pip2net, wire_fanout
* ecp5: Add DCSC supportgatecat2021-07-061-0/+12
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* Fixing old emails and names in copyrightsgatecat2021-06-121-2/+2
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* ecp5: Add missing clock edge assignmentsgatecat2021-06-101-0/+2
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* Add relative constraints to position MULT18X18D near connected ALU54B.Adam Greig2021-04-291-0/+5
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* Replace DelayInfo with DelayPair/DelayQuadgatecat2021-02-191-23/+20
| | | | | | | | | | | | | | | | | This replaces the arch-specific DelayInfo structure with new DelayPair (min/max only) and DelayQuad (min/max for both rise and fall) structures that form part of common code. This further reduces the amount of arch-specific code; and also provides useful data structures for timing analysis which will need to delay with pairs/quads of delays as it is improved. While there may be a small performance cost to arches that didn't separate the rise/fall cases (arches that aren't currently separating the min/max cases just need to be fixed...) in DelayInfo, my expectation is that inlining will mean this doesn't make much difference. Signed-off-by: gatecat <gatecat@ds0.me>
* Merge pull request #568 from YosysHQ/dave/arch-overridegatecat2021-02-081-12/+2
|\ | | | | Create a new BaseArch that formally specifies the Arch API and provides some base implementations
| * Rename ArchBase to BaseArch for consistency with BaseCtxD. Shah2021-02-051-2/+2
| | | | | | | | Signed-off-by: D. Shah <dave@ds0.me>
| * Add default implementation of bel bucket functionsD. Shah2021-02-051-12/+2
| | | | | | | | Signed-off-by: D. Shah <dave@ds0.me>
* | Use RelSlice::ssize instead of cast-to-int throughoutD. Shah2021-02-081-6/+6
|/ | | | Signed-off-by: D. Shah <dave@ds0.me>
* ecp5: Use snake case for arch-specific functionsD. Shah2021-02-031-48/+47
| | | | | | | This makes the difference clearer between the general arch API that everyone must implement; and helper functions specific to one arch. Signed-off-by: D. Shah <dave@ds0.me>
* ecp5: Implement IdStringList for all arch object namesD. Shah2021-02-021-58/+46
| | | | | | | This is a complete implementation of IdStringList for ECP5; excluding the GUI (which you will have to disable for it to build). Signed-off-by: D. Shah <dave@ds0.me>
* ecp5: Proof-of-concept using IdStringList for bel namesD. Shah2021-02-021-3/+12
| | | | | | | | | | | This uses the new IdStringList API to store bel names for the ECP5. Note that other arches and the GUI do not yet build with this proof-of-concept patch. getBelByName still uses the old implementation and could be more efficiently implemented with further development. Signed-off-by: D. Shah <dave@ds0.me>
* Run "make clangformat".Keith Rothman2021-02-021-2/+2
| | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* Rename Partition -> BelBucket.Keith Rothman2021-02-021-3/+3
| | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* Working compile of ECP5.Keith Rothman2021-02-021-1/+1
| | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* Refactor ECP5 to new Partition API.Keith Rothman2021-02-021-0/+13
| | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* cleanup: Remove dead/unused codeD. Shah2021-01-281-25/+0
| | | | | | | Note that some '#if 0' code that might still be useful for debugging in the future has been retained. Signed-off-by: D. Shah <dave@ds0.me>
* ecp5: Switch from RelPtr to RelSliceD. Shah2021-01-271-67/+53
| | | | | | | | | | This replaces RelPtrs and a separate length field with a Rust-style slice containing both a pointer and a length; with bounds checking always enforced. Thus iterating over these structures is both cleaner and safer. Signed-off-by: D. Shah <dave@ds0.me>
* ecp5: Fix FF timing dataDavid Shah2020-12-171-4/+4
| | | | Signed-off-by: David Shah <dave@ds0.me>
* Fix clangformat and execute itMiodrag Milanovic2020-06-271-12/+8
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* Simplify and improve chipdb embedding/loading.whitequark2020-06-261-49/+33
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* CMake: rewrite chipdb handling from ground up.whitequark2020-06-251-2/+2
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* Port nextpnr-{ice40,ecp5} to WASI.whitequark2020-05-231-2/+3
| | | | | | | | | | | | | | | | | | | | | This involves very few changes, all typical to WASM ports: * WASM doesn't currently support threads or atomics so those are disabled. * WASM doesn't currently support exceptions so the exception machinery is stubbed out. * WASM doesn't (and can't) have mmap(), so an emulation library is used. That library currently doesn't support MAP_SHARED flags, so MAP_PRIVATE is used instead. There is also an update to bring ECP5 bbasm CMake rules to parity with iCE40 ones, since although it is possible to embed chipdb into nextpnr on WASM, a 200 MB WASM file has very few practical uses. The README is not updated and there is no included toolchain file because at the moment it's not possible to build nextpnr with upstream boost and wasi-libc. Boost requires a patch (merged, will be available in boost 1.74.0), wasi-libc requires a few unmerged patches.
* ecp5: MULT18X18D timing fixesDavid Shah2020-05-011-10/+26
| | | | Signed-off-by: David Shah <dave@ds0.me>
* No cell delay for clocked MULT18X18DRoss Schlaikjer2020-04-301-0/+2
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* Issue warning for mixed-mode inputsRoss Schlaikjer2020-04-291-24/+11
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* Handle register timing caseRoss Schlaikjer2020-04-291-6/+58
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* Use registered port class on mult18x18Ross Schlaikjer2020-04-291-3/+5
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* Alter MULT18X18D timing db based on register configRoss Schlaikjer2020-04-281-1/+1
| | | | | | | | | | | | | | | If the REG_INPUTA_CLK and REG_INPUTB_CLK values are set, then we should use the faster setup/hold timings for the 18x8 multiplier. Similarly, check the value of REG_OUTPUT_CLK for whether or not to use faster timings for the output. This is based on how I currently understand the registers to work - if anyone knows the actual rules for when each timing applies please do chime in to correct this implementation if necessary. Along the same lines, this PR does not address the case when the pipeline registers are enabled, since it is not clear to me how exactly that affects the timing.
* Merge pull request #423 from rschlaikjer/rschlaikjer-regmode-timing-databaseDavid Shah2020-04-071-4/+2
|\ | | | | Add support for REGMODE to DP16KD
| * Actually just move all the logic to ArchInfoRoss Schlaikjer2020-04-071-15/+2
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| * Extract regmode configuration to ArchInfoRoss Schlaikjer2020-04-071-8/+4
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| * Change timing database lookup based on REGMODE valueRoss Schlaikjer2020-04-071-4/+19
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* | ecp5: Proper support for '12k' deviceDavid Shah2020-03-131-2/+7
|/ | | | Signed-off-by: David Shah <dave@ds0.me>
* router2: Improve flow and log outputDavid Shah2020-02-031-1/+1
| | | | Signed-off-by: David Shah <dave@ds0.me>
* Allow selection of router algorithmDavid Shah2020-02-031-2/+16
| | | | Signed-off-by: David Shah <dave@ds0.me>
* router2: Make magic numbers configurableDavid Shah2020-02-031-1/+1
| | | | Signed-off-by: David Shah <dave@ds0.me>
* ecp5: Improve bounding box accuracyDavid Shah2020-02-031-4/+19
| | | | Signed-off-by: David Shah <dave@ds0.me>
* ecp5: router2 main renameDavid Shah2020-02-031-1/+1
| | | | Signed-off-by: David Shah <dave@ds0.me>
* ecp5: Router2 test integrationDavid Shah2020-02-031-1/+38
| | | | Signed-off-by: David Shah <dave@ds0.me>
* Merge remote-tracking branch 'origin/master' into mmicko/ecp5_guiMiodrag Milanovic2019-12-281-1/+11
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| * ecp5: Add an error for out-of-sync constids and bbaDavid Shah2019-10-261-0/+3
| | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
| * ecp5: Fix routing to shared DSP control inputsDavid Shah2019-10-251-1/+8
| | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
* | move bel creation to gfx.ccMiodrag Milanovic2019-12-151-122/+2
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* | fix formatingMiodrag Milanovic2019-12-141-2/+1
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* | more new wires addedMiodrag Milanovic2019-12-141-1/+10
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