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| | * ice40: Preserve top level IO properlyDavid Shah2019-10-191-2/+2
| | * ecp5: Preserve top level IO properlyDavid Shah2019-10-182-12/+22
| * | ecp5: Copy timing constraints across ECLKBRIDGECSDavid Shah2019-11-011-1/+4
| * | ecp5: Fix placement of ECLKBRIDGECSDavid Shah2019-11-011-11/+41
| * | ecp5: Allow setting drive strength for 3V3 IOsDavid Shah2019-10-261-0/+10
| * | ecp5: Add constids for new timing cell typesDavid Shah2019-10-262-0/+10
| * | ecp5: Add an error for out-of-sync constids and bbaDavid Shah2019-10-264-2/+10
| * | ecp5: Fix routing to shared DSP control inputsDavid Shah2019-10-253-1/+37
| * | ecp5: Make database build depend on constids.incDavid Shah2019-10-201-2/+2
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* | add newline at eofMiodrag Milanovic2019-12-281-1/+1
* | optimize and set orderMiodrag Milanovic2019-12-201-276/+236
* | clang formatMiodrag Milanovic2019-12-202-47/+132
* | Add all missing wiresMiodrag Milanovic2019-12-201-1/+1556
* | Add global wiresMiodrag Milanovic2019-12-154-19/+138
* | more pips on connection boxMiodrag Milanovic2019-12-151-0/+9
* | cleanup and formatingMiodrag Milanovic2019-12-152-13/+13
* | make it more simetricMiodrag Milanovic2019-12-151-13/+14
* | optimize and add some missing pipsMiodrag Milanovic2019-12-151-28/+17
* | cleanupMiodrag Milanovic2019-12-151-12/+7
* | cleanup wireMiodrag Milanovic2019-12-151-110/+3
* | move bel creation to gfx.ccMiodrag Milanovic2019-12-153-122/+101
* | fix formatingMiodrag Milanovic2019-12-143-110/+138
* | lot more pipsMiodrag Milanovic2019-12-141-4/+51
* | fixes and more pipsMiodrag Milanovic2019-12-142-1/+92
* | pips for alu, mult and memoryMiodrag Milanovic2019-12-141-3/+43
* | pips for iosMiodrag Milanovic2019-12-142-7/+134
* | propagate w and hMiodrag Milanovic2019-12-141-60/+96
* | pips for other type of connection boxMiodrag Milanovic2019-12-141-5/+17
* | more new wires addedMiodrag Milanovic2019-12-145-2/+214
* | ebr, mult and alu nice displayMiodrag Milanovic2019-12-142-8/+15
* | add moreMiodrag Milanovic2019-12-133-4/+44
* | new wires in dbMiodrag Milanovic2019-12-133-20/+498
* | added siologicMiodrag Milanovic2019-12-134-2/+63
* | Add many new wiresMiodrag Milanovic2019-12-134-0/+1250
* | clangformat runMiodrag Milanovic2019-12-083-329/+364
* | display IOs properlyMiodrag Milanovic2019-12-071-21/+5
* | More bels show properlyMiodrag Milanovic2019-12-071-43/+82
* | add dcca bels and dummy parts for other belsMiodrag Milanovic2019-12-071-9/+54
* | Fix edge wiresMiodrag Milanovic2019-12-071-69/+108
* | add more pipsMiodrag Milanovic2019-12-011-0/+49
* | Handle H00 and V00Miodrag Milanovic2019-11-111-6/+49
* | More pips and fix for V01Miodrag Milanovic2019-11-111-42/+170
* | cleanupMiodrag Milanovic2019-11-111-174/+78
* | proper h06 and v06Miodrag Milanovic2019-11-111-34/+39
* | More pips addedMiodrag Milanovic2019-11-101-41/+200
* | more pips, and valid mappingMiodrag Milanovic2019-11-102-10/+23
* | Fixed V2, some more pipsMiodrag Milanovic2019-11-101-12/+43
* | more pipsMiodrag Milanovic2019-11-101-2/+43
* | Draw some pips, fixed H6 and V6Miodrag Milanovic2019-11-093-31/+58
* | Show V02/V06/H02/H06Miodrag Milanovic2019-10-253-13/+105
generated by cgit v1.2.3 (git 2.25.1) at 2024-07-08 17:15:32 +0000