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* archapi: Use arbitrary rather than actual placement in predictDelaygatecat2021-12-192-14/+9
* ecp5: LUT permutation supportgatecat2021-12-137-7/+117
* ecp5: Reduce some chipdb fields sizesMatt Johnston2021-12-132-14/+15
* clangformatgatecat2021-12-121-4/+6
* ecp5: Use a vector rather than dictMatt Johnston2021-12-123-14/+106
* ecp5: Fix packing of IOFF with IODELAYsgatecat2021-11-052-3/+11
* Fix mistype.YRabbit2021-09-291-1/+1
* clangformatgatecat2021-08-241-5/+5
* Merge pull request #798 from kleinai/extref-locgatecat2021-08-191-6/+44
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| * Make EXTREFB handling more robustAidan Klein2021-08-181-6/+44
* | clangformatgatecat2021-08-141-2/+3
* | ecp5: Enable OPENDRAIN on differential outputsGreg Davill2021-08-141-1/+13
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* ecp5: Copy REGMODE in PDP mode to both A and B portsgatecat2021-08-021-1/+4
* ecp5: Add DCSC supportgatecat2021-07-064-11/+55
* Fixing old emails and names in copyrightsgatecat2021-06-1221-27/+27
* ecp5: Add missing clock edge assignmentsgatecat2021-06-101-0/+2
* ecp5: Don't attempt to promote undriven nets to globalsgatecat2021-06-071-1/+2
* Remove redundant code after hashlib movegatecat2021-06-021-70/+0
* Use hashlib in most remaining codegatecat2021-06-021-2/+2
* Using hashlib in archesgatecat2021-06-027-49/+33
* Use hashlib in placersgatecat2021-06-021-9/+0
* Use hashlib for core netlist structuresgatecat2021-06-026-81/+80
* Add hash() member functionsgatecat2021-06-021-0/+7
* ecp5: Use new cluster APIgatecat2021-05-063-20/+29
* clangformatgatecat2021-04-301-40/+30
* Only set CIBOUT_BYP on MULTs that are not feeding an ALU.Adam Greig2021-04-291-1/+1
* Add check_alu to Ecp5PackerAdam Greig2021-04-291-15/+123
* Add relative constraints to position MULT18X18D near connected ALU54B.Adam Greig2021-04-292-0/+29
* Add ALU54B.REG_OPCODEOP1_1_CLK parameter supportAdam Greig2021-04-291-0/+2
* Split nextpnr.h to allow for linear inclusion.Keith Rothman2021-03-153-10/+21
* timing: Replace all users of criticality with new enginegatecat2021-03-041-9/+3
* Fix compiler warnings introduced by -Wextragatecat2021-02-252-2/+1
* Replace DelayInfo with DelayPair/DelayQuadgatecat2021-02-194-86/+48
* Remove isValidBelForCellgatecat2021-02-164-58/+32
* Add getBelHidden and add some missing "override" statements.Keith Rothman2021-02-111-1/+1
* Add BaseArchRanges for default ArchRanges typesgatecat2021-02-091-16/+1
* Merge pull request #568 from YosysHQ/dave/arch-overridegatecat2021-02-084-268/+116
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| * Use 'T' postfix to disambiguate LHS and RHS of usingD. Shah2021-02-081-21/+21
| * Add archArgs and archArgsToId to Arch APID. Shah2021-02-051-2/+3
| * Rename ArchBase to BaseArch for consistency with BaseCtxD. Shah2021-02-052-6/+6
| * Add default implementation of bel bucket functionsD. Shah2021-02-054-83/+5
| * Add default implementation of some range-returning functionsD. Shah2021-02-051-12/+0
| * Add a few more functions to ArchBaseD. Shah2021-02-051-3/+4
| * ecp5: Use common wire/pip bindingD. Shah2021-02-051-82/+6
| * nextpnr: Use templates to specify range typesD. Shah2021-02-051-18/+46
| * nextpnr: Add base virtual functions for non-range Arch APID. Shah2021-02-051-84/+68
* | Use RelSlice::ssize instead of cast-to-int throughoutD. Shah2021-02-082-10/+10
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* ecp5: Use snake case for arch-specific functionsD. Shah2021-02-038-310/+310
* ecp5: Implement IdStringList for all arch object namesD. Shah2021-02-024-85/+66
* refactor: Replace getXName().c_str(ctx) with ctx->nameOfXD. Shah2021-02-022-8/+7
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