index
:
iCE40/nextpnr
master
[no description]
about
summary
refs
log
tree
commit
diff
stats
log msg
author
committer
range
path:
root
/
ecp5
Commit message (
Expand
)
Author
Age
Files
Lines
*
ecp5: Fix PDPW16K clock param renaming
gatecat
2022-02-28
1
-1
/
+1
*
refactor: New member functions to replace design_utils
gatecat
2022-02-18
5
-238
/
+238
*
refactor: Use constids instead of id("..")
gatecat
2022-02-16
11
-1318
/
+1674
*
refactor: Use cell member functions to add ports
gatecat
2022-02-16
1
-85
/
+79
*
refactor: New NetInfo and CellInfo constructors
gatecat
2022-02-16
3
-63
/
+36
*
archapi: Use arbitrary rather than actual placement in predictDelay
gatecat
2021-12-19
2
-14
/
+9
*
ecp5: LUT permutation support
gatecat
2021-12-13
7
-7
/
+117
*
ecp5: Reduce some chipdb fields sizes
Matt Johnston
2021-12-13
2
-14
/
+15
*
clangformat
gatecat
2021-12-12
1
-4
/
+6
*
ecp5: Use a vector rather than dict
Matt Johnston
2021-12-12
3
-14
/
+106
*
ecp5: Fix packing of IOFF with IODELAYs
gatecat
2021-11-05
2
-3
/
+11
*
Fix mistype.
YRabbit
2021-09-29
1
-1
/
+1
*
clangformat
gatecat
2021-08-24
1
-5
/
+5
*
Merge pull request #798 from kleinai/extref-loc
gatecat
2021-08-19
1
-6
/
+44
|
\
|
*
Make EXTREFB handling more robust
Aidan Klein
2021-08-18
1
-6
/
+44
*
|
clangformat
gatecat
2021-08-14
1
-2
/
+3
*
|
ecp5: Enable OPENDRAIN on differential outputs
Greg Davill
2021-08-14
1
-1
/
+13
|
/
*
ecp5: Copy REGMODE in PDP mode to both A and B ports
gatecat
2021-08-02
1
-1
/
+4
*
ecp5: Add DCSC support
gatecat
2021-07-06
4
-11
/
+55
*
Fixing old emails and names in copyrights
gatecat
2021-06-12
21
-27
/
+27
*
ecp5: Add missing clock edge assignments
gatecat
2021-06-10
1
-0
/
+2
*
ecp5: Don't attempt to promote undriven nets to globals
gatecat
2021-06-07
1
-1
/
+2
*
Remove redundant code after hashlib move
gatecat
2021-06-02
1
-70
/
+0
*
Use hashlib in most remaining code
gatecat
2021-06-02
1
-2
/
+2
*
Using hashlib in arches
gatecat
2021-06-02
7
-49
/
+33
*
Use hashlib in placers
gatecat
2021-06-02
1
-9
/
+0
*
Use hashlib for core netlist structures
gatecat
2021-06-02
6
-81
/
+80
*
Add hash() member functions
gatecat
2021-06-02
1
-0
/
+7
*
ecp5: Use new cluster API
gatecat
2021-05-06
3
-20
/
+29
*
clangformat
gatecat
2021-04-30
1
-40
/
+30
*
Only set CIBOUT_BYP on MULTs that are not feeding an ALU.
Adam Greig
2021-04-29
1
-1
/
+1
*
Add check_alu to Ecp5Packer
Adam Greig
2021-04-29
1
-15
/
+123
*
Add relative constraints to position MULT18X18D near connected ALU54B.
Adam Greig
2021-04-29
2
-0
/
+29
*
Add ALU54B.REG_OPCODEOP1_1_CLK parameter support
Adam Greig
2021-04-29
1
-0
/
+2
*
Split nextpnr.h to allow for linear inclusion.
Keith Rothman
2021-03-15
3
-10
/
+21
*
timing: Replace all users of criticality with new engine
gatecat
2021-03-04
1
-9
/
+3
*
Fix compiler warnings introduced by -Wextra
gatecat
2021-02-25
2
-2
/
+1
*
Replace DelayInfo with DelayPair/DelayQuad
gatecat
2021-02-19
4
-86
/
+48
*
Remove isValidBelForCell
gatecat
2021-02-16
4
-58
/
+32
*
Add getBelHidden and add some missing "override" statements.
Keith Rothman
2021-02-11
1
-1
/
+1
*
Add BaseArchRanges for default ArchRanges types
gatecat
2021-02-09
1
-16
/
+1
*
Merge pull request #568 from YosysHQ/dave/arch-override
gatecat
2021-02-08
4
-268
/
+116
|
\
|
*
Use 'T' postfix to disambiguate LHS and RHS of using
D. Shah
2021-02-08
1
-21
/
+21
|
*
Add archArgs and archArgsToId to Arch API
D. Shah
2021-02-05
1
-2
/
+3
|
*
Rename ArchBase to BaseArch for consistency with BaseCtx
D. Shah
2021-02-05
2
-6
/
+6
|
*
Add default implementation of bel bucket functions
D. Shah
2021-02-05
4
-83
/
+5
|
*
Add default implementation of some range-returning functions
D. Shah
2021-02-05
1
-12
/
+0
|
*
Add a few more functions to ArchBase
D. Shah
2021-02-05
1
-3
/
+4
|
*
ecp5: Use common wire/pip binding
D. Shah
2021-02-05
1
-82
/
+6
|
*
nextpnr: Use templates to specify range types
D. Shah
2021-02-05
1
-18
/
+46
[next]