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* ecp5: Constraint checker and placer for DQSBUFMDavid Shah2019-02-241-1/+57
* ecp5: Add OSHX2A supportDavid Shah2019-02-241-0/+26
* ecp5: Add IDDRX2F supportDavid Shah2019-02-241-2/+25
* ecp5: Packing of ODDRX2FDavid Shah2019-02-243-5/+119
* ecp5: Helper functions for DQS and ECLKDavid Shah2019-02-245-1/+153
* ecp5: Add timing data for DQS-related cellsDavid Shah2019-02-241-0/+27
* ecp5: Add DQS groupings to databaseDavid Shah2019-02-242-4/+15
* ecp5: Fix typoDavid Shah2019-02-141-0/+1
* Merge pull request #228 from YosysHQ/ecp5_embed_baseDavid Shah2019-02-143-4/+2683
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| * ecp5: Add --basecfg deprecation warningDavid Shah2019-02-081-2/+11
| * ecp5: Embed baseconfigDavid Shah2019-02-082-2/+2672
* | Merge branch 'master' into mmaped_chipdbMiodrag Milanović2019-02-122-5/+33
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| * | ecp5: Fix global routing performanceDavid Shah2019-02-121-1/+22
| * | ecp5: cmake: Search for pytrellis.so in multiple locationsGabriel L. Somlo2019-02-101-4/+11
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* | Fix according to comments on PRMiodrag Milanovic2019-02-101-1/+1
* | Load chipdb from filesystem as optionMiodrag Milanovic2019-02-093-65/+93
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* Merge branch 'ecp5func'David Shah2019-02-084-1/+156
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| * ecp5: Adding DTR, OSCG, CLKDIVF, USRMCLK, JTAGGDavid Shah2019-02-084-1/+156
* | Merge pull request #210 from twam/masterDavid Shah2019-01-271-3/+3
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| * Search for trellis in /usr/local/share/trellis if not specified with -DTRELLI...Tobias Müller2019-01-131-3/+3
* | Make cross compile possible for mingwMiodrag Milanovic2019-01-271-1/+1
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* ecp5: Add PULLMODE supportDavid Shah2019-01-071-0/+2
* ecp5: Check for incorrect use of TRELLIS_IO 'B' pinDavid Shah2018-12-251-0/+9
* ecp5: Fix tristate IO insertionDavid Shah2018-12-221-1/+1
* ecp5: Fix ODDR when used with manually instantiated TRELLIS_IODavid Shah2018-12-191-0/+4
* ecp5: Fix IOLOGIC ports at the same constant valueDavid Shah2018-12-151-2/+12
* ecp5: Add IOLOGIC timing and bitstream; ODDR workingDavid Shah2018-12-144-24/+71
* ecp5: Add ODDR packingDavid Shah2018-12-142-1/+25
* ecp5: Adding IOLOGIC packingDavid Shah2018-12-142-11/+109
* ecp5: Add {S}IOLOGIC constids and cellDavid Shah2018-12-122-0/+86
* Merge pull request #159 from YosysHQ/ecp5_pllplaceDavid Shah2018-12-012-2/+59
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| * ecp5: Pre-place PLLs and use dedicated routes into globalsDavid Shah2018-11-302-2/+59
* | Improve reporting of unknown cell typesDavid Shah2018-11-291-1/+2
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* ecp5: Fix UR PLL tile coordinatesDavid Shah2018-11-261-2/+2
* Merge pull request #143 from daveshah1/ecp5_muxesDavid Shah2018-11-265-6/+169
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| * ecp5: Add support for LUT7 muxDavid Shah2018-11-181-6/+116
| * ecp5: More optimal LUT6 placementDavid Shah2018-11-163-1/+11
| * ecp5: Adding mux support up to LUT6David Shah2018-11-163-6/+49
* | python: Fixes to get net wires map workingDavid Shah2018-11-221-2/+24
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* ecp5: Add 10% safety margin to pip delaysDavid Shah2018-11-161-2/+2
* ecp5: clangformat timing changesDavid Shah2018-11-163-17/+18
* ecp5: Use speed-grade-specific delay estimateDavid Shah2018-11-161-2/+2
* ecp5: Fix db import, improve timing data debuggingDavid Shah2018-11-163-4/+40
* ecp5: Allow selection of device speed gradeDavid Shah2018-11-161-3/+26
* ecp5: Post-rebase fixDavid Shah2018-11-161-3/+3
* ecp5: Consider fanout when calculating pip delaysDavid Shah2018-11-161-2/+12
* ecp5: Fix timing pip classesDavid Shah2018-11-161-1/+1
* ecp5: Use new timing dataDavid Shah2018-11-164-94/+82
* ecp5: Fix timing data importDavid Shah2018-11-161-5/+16
* ecp5: Adding real timing data to databaseDavid Shah2018-11-166-49/+202
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