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* Added more code comments, formatted the codeMaciej Kurc2021-07-221-2/+3
* LUT mapping ceche optimizations 2Maciej Kurc2021-07-161-80/+0
* Working site LUT mapping cacheMaciej Kurc2021-07-161-15/+92
* Using hashlib in archesgatecat2021-06-021-7/+7
* clangformatgatecat2021-04-121-7/+4
* [interchange] Prevent site router from generating incorrect LUTs.Keith Rothman2021-04-061-6/+12
* [interchange] Add crude pseudo pip model.Keith Rothman2021-04-061-1/+41
* Add some FIXME's around VCC assumption in LUT logic.Keith Rothman2021-03-251-0/+17
* Re-work LUT mapping logic to only put VCC pins when required.Keith Rothman2021-03-251-5/+111
* Refactor header structures in FPGA interchange Arch.Keith Rothman2021-03-191-1/+17
* Use NEXTPNR_NAMESPACE macro's now that headers are seperated.Keith Rothman2021-03-151-1/+1
* clangformatgatecat2021-03-031-92/+86
* Initial LUT rotation logic.Keith Rothman2021-02-261-0/+370