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path: root/fpga_interchange/site_router.cc
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* interchange: pseudo pips: fix illegal tile pseudo PIPsAlessandro Comodi2021-05-141-6/+24
* interchange: site router: add valid pips list to check during routingAlessandro Comodi2021-05-131-0/+43
* interchange: site router: fix log messagesAlessandro Comodi2021-05-101-3/+3
* interchange: site router: fix illegal site thru pathsAlessandro Comodi2021-05-101-0/+12
* Hash table refactoringgatecat2021-04-141-4/+4
* clangformatgatecat2021-04-121-10/+12
* [interchange] Fix invalid use of local variables due to refactoring.Keith Rothman2021-04-061-6/+1
* [interchange] Prevent site router from generating incorrect LUTs.Keith Rothman2021-04-061-34/+86
* [interchange] Add some documentation for the site router.Keith Rothman2021-04-051-10/+58
* interchange: Fix bug in site router where a bad solution isn't remove.Keith Rothman2021-03-251-3/+7
* Implement debugging tools for site router.Keith Rothman2021-03-251-13/+67
* Add initial handling of local site inverters and constant signals.Keith Rothman2021-03-251-31/+294
* [FPGA interchange] Small fix to get_net_type.Keith Rothman2021-03-251-6/+6
* Merge pull request #640 from litghost/inversion_logicgatecat2021-03-231-8/+18
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| * Initial version of inverter logic.Keith Rothman2021-03-231-8/+18
* | interchange: Add nice error for missing cell pinsgatecat2021-03-231-0/+3
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* Rework FPGA interchange site router.Keith Rothman2021-03-221-567/+528
* For now just return false in the site router.Keith Rothman2021-02-261-1/+1
* Initial LUT rotation logic.Keith Rothman2021-02-261-5/+30
* Fix assorted bugs in FPGA interchange.Keith Rothman2021-02-231-10/+76
* Add initial logic for handling dedicated interconnect situations.Keith Rothman2021-02-231-0/+6
* Do some spell checking on site_router.ccKeith Rothman2021-02-181-18/+18
* Add some utility methods for site instance access.Keith Rothman2021-02-181-6/+3
* Add initial site router.Keith Rothman2021-02-171-0/+753