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* Add getBelHidden and add some missing "override" statements.Keith Rothman2021-02-111-2/+1
* interchange: Base on ArchAPID. Shah2021-02-082-106/+135
* Add RelSlice::ssize and use it when comparing with signed ints.Keith Rothman2021-02-052-27/+28
* Move all string data into BBA file.Keith Rothman2021-02-054-48901/+15
* Use RelSlice instead of RelPtr in cases where sizes are present.Keith Rothman2021-02-042-97/+67
* Update APIs to conform to style guide.Keith Rothman2021-02-045-67/+48939
* Remove unused method getReservedWireNet.Keith Rothman2021-02-041-7/+0
* Update copywrite headers.Keith Rothman2021-02-046-4/+10
* Correct some typos.Keith Rothman2021-02-041-4/+4
* Fix warnings with signed/unsigned.Keith Rothman2021-02-041-1/+1
* Fix fpga_interchange/README.md duplicate patch statement.Keith Rothman2021-02-041-8/+0
* Fix URLs in Markdown.Keith Rothman2021-02-041-2/+2
* Add empty constids.inc for build.Keith Rothman2021-02-041-0/+0
* Run "make clangformat".Keith Rothman2021-02-044-148/+100
* Add README about initial state of FPGA interchange implementation.Keith Rothman2021-02-041-0/+170
* Update FPGA interchange to use IdStringList.Keith Rothman2021-02-042-132/+137
* Start adding data for placement constraint solving.Keith Rothman2021-02-042-50/+43
* Debug BEL bucket data.Keith Rothman2021-02-041-11/+14
* Add initial updates to FPGA interchange arch for BEL buckets.Keith Rothman2021-02-045-0/+247
* Address review comments.Keith Rothman2021-02-043-95/+6
* Fix BBA import bugs.Keith Rothman2021-02-042-69/+201
* Assorted fixes to new FPGA interchange based arch.Keith Rothman2021-02-043-5/+13
* Initial compiling version.Keith Rothman2021-02-042-16/+25
* Initial FPGA interchange (which is just a cut-down xilinx arch).Keith Rothman2021-02-049-0/+2102