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* gowin: improve clock wire routingYRabbit2022-12-301-5/+5
| | | | | | | | | | | | | | The dedicated router for clock wires now understands not only the IO pins but also the rPLL outputs as clock sources. This simple router sets an optimal route, so it is now the default router. It can be disabled with the --disable-globals command line flag if desired, but this is not recommended due to possible clock skew. Still for GW1N-4C there is no good router for clock wires as there external quartz resonator is connected via PLL. Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
* gowin: add a separate router for the clocksYRabbit2022-06-231-1/+15
| | | | | | | | | | | | | | | | | | | | | | | A simple router that takes advantage of the fact that in each cell with DFFs their CLK inputs can directly connect to the global clock network. Networks with a large number of such sinks are sought and then each network is assigned to the available independent global clock networks. There are limited possibilities for routing mixed networks, that is, when the sinks are not only CLKs: in this case an attempt is made to use wires such as SN10/20 and EW10/20, that is, one short transition can be added between the global clock network and the sink. * At this time, networks with a source other than the I/O pin are not supported. This is typical for Tangnano4k and runber boards. * Router is disabled by default, you need to specify option --enable-globals to activate * No new chip bases are required. This may change in the distant future. Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
* gowin: don't crash if no arguments are setYRabbit2022-03-161-0/+4
| | | | Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
* Set the locale as early as possibleYRabbit2022-03-161-9/+0
| | | | Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
* gowin: test locale workaroundYRabbit2022-03-151-1/+5
| | | | Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
* gowin: support for locales other than en_US and CYRabbit2022-03-141-0/+6
| | | | | | | Specifically, those locales where the fractional part separator in floating point numbers is not a dot. Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
* gowin: recognize partnumbers of GW1NZ-1YRabbit2022-02-241-1/+1
| | | | | | | | | | | The model should be recognized by the partnumber, --family is needed only if the same partnumbers belong to different models. This is done in order to automatically generate parameters for calling nextpnr from Gowin files without problems: there also only partnumber is used and only in some cases the model is specified with the -name parameter and GW1NZ-1 is not such a case. Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
* clangformatgatecat2022-02-161-7/+7
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* gowin: add an option to manually specify familyIcenowy Zheng2022-02-061-6/+11
| | | | | | | | | | | In the vendor IDE, there's a device family named GW1N-9C (which seems to mean C revision of GW1N-9), in which the model numbers are all the same with GW1N-9. Add an option to nextpnr-gowin to allow manually specified family for this situation. Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
* gowin: Add GUI.YRabbit2022-01-291-0/+1
| | | | | | | | | | | | | | | * Items such as LUT, DFF, MUX, ALU, IOB are displayed; * Local wires, 1-2-4-8 wires are displayed; * The clock spines, taps and branches are displayed with some caveats. For now, you can not create a project in the GUI because of possible conflict with another PR (about GW1NR-9C support), but you can specify the board in the command line and load .JSON and .CST in the GUI. Although ALUs are displayed, but the CIN and COUT wires are not. This is still an unsolved problem. Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
* Clean gowin modification regexuis2021-12-181-6/+2
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* gowin: Recognize models correctlyYRabbit2021-12-151-1/+1
| | | | | | | | | | | For example, clearly distinguish between GW1N-4 GW1NR-4 GW1NS-4 GW1NSR-4 GW1NSR-4 Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
* gowin: Use speed from chip base.YRabbit2021-11-051-4/+1
| | | | | | | Another simplification of the input regular expression, now the speed is taken from the base. Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
* gowin: Add partnumbers and packages to the chipdbYRabbit2021-11-041-1/+1
| | | | | | | | | | Instead of parsing the partnumber with a regular expression, a simple table is used. This is done because the structure of the partnumber changes as new features appear (e.g., ES instead of C6/I5) This commit does not yet disable the very first regular expression check. Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
* clangformatgatecat2021-07-211-1/+1
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* GW1NR is not a seperate family, but GW1NS isPepijn de Vos2021-07-111-1/+8
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* clangformatgatecat2021-07-081-2/+1
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* add support for GW1NS-2 familyGwenhael Goavec-Merou2021-07-061-5/+6
| | | | Signed-off-by: Gwenhael Goavec-Merou <gwenhael.goavec-merou@trabucayre.com>
* Fixing old emails and names in copyrightsgatecat2021-06-121-1/+1
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* Use hashlib in most remaining codegatecat2021-06-021-2/+2
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* Fix compiler warnings introduced by -Wextragatecat2021-02-251-3/+3
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* clangformatDavid Shah2020-12-301-1/+1
| | | | Signed-off-by: David Shah <dave@ds0.me>
* Gowin target (#542)Pepijn de Vos2020-12-301-0/+90
* load wires * add slice bels * add IOB * add aliases * local aliases * broken packing stuff * working packer * add constraints * pnr runs1111 * add timing info * constraints * more constraint stuff * add copyright * remove generic reference * remove parameters * remove generic python api * add newline to end of file * some small refactoring * warn on invalid constraints * don't error on missing cell * comment out debugging print * typo * avoid copy * faster empty idstring * remove intermediate variable * no more deadnames * fix cst warnings * increase ripup and epsilon a bit * take single device parameter * add info to readme * gui stubs * Revert 4d03b681a8634e978bd5af73c97665500047e055 * assign ff_used in assignArchInfo * decrease beta for better routability * try to fix CI
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