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* gowin: Add PLL support for the GW1NR-9C chipYRabbit2023-01-261-15/+9
| | | | | | | | | | | | | | | | | | | | This chip is used in the Tangnano9k board. * all parameters of the rPLL primitive are supported; * all PLL outputs are treated as clock sources and optimized routing is applied to them; * primitive rPLL on different chips has a completely different structure: for example in GW1N-1 it takes two cells, and in GW1NR-9C as many as four, despite this unification was carried out and different chips are processed by the same functions, but this led to the fact that you can not use the PLL chip GW1N-1 with the old apicula bases - will issue a warning and refuse to encode primitive. In other cases compatibility is supported. * Cosmetic change: the usage report shows the rPLL names without any service bels. * I use ctx->idf() on occasion, it's not a total redesign. Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
* gowin: improve error messageYRabbit2023-01-191-1/+2
| | | | Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
* gowin: add a PLL primitive for the GW1NS-4 seriesYRabbit2023-01-181-24/+45
| | | | | | | | | | * both instances of the new PLLVR type are supported; * primitive placement is optimized for the use of dedicated PLL clock pins; * all 4 outputs of each primitive can use the clock nets (only 5 lines in total at the same time so far). Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
* gowin: BUGFIX: Correctly handle resetsYRabbit2022-12-091-0/+14
| | | | | | | | | | When a single primitive occupies several cells, care must be taken when manipulating the parameters of that primitive: when creating cells, each cell must receive a copy of all the parameters and not modify them unnecessarily. That is, if possible, it is better to make all parameter changes before dividing the primitive into cells. Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
* gowin: add PLL pins processingYRabbit2022-12-041-6/+5
| | | | | | | | | | | Uses the information of the special input pins for the PLL in the current chip. If such pins are involved, no routing is performed and information about the use of implicit wires is passed to the packer. The RESET and RESET_P inputs are now also disabled if they are connected to VSS/VCC. Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
* gowin: mark the PLL ports that are not in useYRabbit2022-11-201-0/+8
| | | | | | | Unused ports are deactivated by special fuse combinations, rather than being left dangling in the air. Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
* gowin: add support for a more common chipYRabbit2022-11-121-1/+1
| | | | | | | | The GW1N-1 and GW1NZ-1 have a similar PLL, but the board with the former chip is already very hard to buy, so let's experiment with a more affordable chip. Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
* gowin: add initial PLL supportYRabbit2022-11-101-0/+72
| | | | | | | | | | | The rPLL primitive for the simplest chip (GW1N-1) in the family is processed. All parameters of the primitive are passed on to gowin_pack, and general-purpose wires are used for routing outputs of the primitive. Compatible with older versions of apicula, but in this case will refuse to place the new primitive. Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
* refactor: id(stringf(...)) to new idf(...) helpergatecat2022-08-101-1/+1
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* gowin: Remove incomprehensible names of the muxesYRabbit2022-07-191-12/+9
| | | | | | | | | | | | There is no need to multiply item names, it is a rudiment of my very first addition to nextpnr. Fully compatible with older versions of Apicula. Note: the cosmetic changes in lines with RAM are not my initiative, but the result of applying clang-format. Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
* Merge branch 'master' into clock-wipYRabbit2022-07-051-0/+90
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| * use DFF RAM modePepijn de Vos2022-07-021-1/+4
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| * Merge branch 'master' into shadowramPepijn de Vos2022-07-021-3/+5
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| * | hook up CE maybePepijn de Vos2022-06-161-0/+1
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| * | lutram actually PnRsPepijn de Vos2022-06-061-1/+4
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| * | WIP shadowramPepijn de Vos2022-06-051-0/+83
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* | | gowin: Let the placer know about global networksYRabbit2022-07-041-0/+4
| |/ |/| | | | | | | | | | | | | | | | | | | Refactor in order to detect networks that will be routed in a special mode earlier. This makes it possible to mark the source of such networks as a global buffer, thereby removing their influence on element placement. In addition, timing classes are set for some cells. Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
* | gowin: Add support for long wiresYRabbit2022-05-271-3/+5
|/ | | | | | | | | | | | | | | | | | | | | | Gowin chips have a highly sophisticated system of long wires that are wired to each cell and allow the clock or logic to spread quickly. This commit implements some of the capabilities of the long wire system for quadrants, leaving out the fine-tuning of them for each column. To make use of the long wire system, the specified wire is cut at the driver and a special cell is placed between the driver and the rest of the wire. * VCC and GND can not use long wires because they are in every cell and there is no point in using a net * Long wire numbers can be specified manually or assigned automatically. * The route from the driver to the port of the new cell can be quite long, this will have to be solved somehow. * It might make sense to add a mechanism for automatically finding candidates for long wires. Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
* gowin: handle the GW1N-9 feature.YRabbit2022-04-031-0/+19
| | | | | | | | This chip has a different default state for one type of I/O buffer --- you have to explicitly switch it to the normal state by feeding VCC/VSS to certain inputs. Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
* gowin: Consider the peculiarity of GW1BR-9CYRabbit2022-03-261-0/+7
| | | | | | | The GW1NR-9C chip ODDR implementation differs from all other supported chips by two suspicious inputs. Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
* Gowin: use global VCC and VSS nets (#956)Pepijn de Vos2022-03-191-9/+6
| | | | | | | * use global VCC and VSS nets * derp * remove init parameter
* gowin: add support for ODDR primitiveYRabbit2022-03-151-4/+98
| | | | | | | | | Compatible with older versions of apicula bases. Also small fixes and as the number of virtual Bels grows it is necessary to assign them Z coordinate in a centralized way to avoid conflicts and for this purpose introduced the BelZ enum. Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
* gowin: Add the Global Set/Reset primitiveYRabbit2022-03-121-0/+36
| | | | | | | | | GSR is added automatically if it was not instantiated by the user explicitly. Compatible with old apicula bases, the functionality does not work, but the crash does not happen --- just a warning. Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
* Switch to potentially-sparse net users arraygatecat2022-02-271-5/+6
| | | | | | | | This uses a new data structure for net.users that allows gaps, so removing a port from a net is no longer an O(n) operation on the number of users the net has. Signed-off-by: gatecat <gatecat@ds0.me>
* gowin: Add support for true differential outputYRabbit2022-02-231-0/+82
| | | | | | | | | The new primitive appears as an amalgamation of two existing OBUF primitives. Compatible with older versions of apicula, although, of course, using TLVDS_OBUF with old databases will not bring the desired result, but no crash. Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
* refactor: New member functions to replace design_utilsgatecat2022-02-181-33/+33
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* refactor: Use constids instead of id("..")gatecat2022-02-161-30/+30
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* refactor: New NetInfo and CellInfo constructorsgatecat2022-02-161-4/+2
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* gowin: Add simplified IO cells processingYRabbit2021-12-201-2/+21
| | | | | | | | | | | | | | | Some models have I/O cells that are IOBUFs, and other types (IBUFs and OBUFs) are obtained by feeding 1 or 0 to the OEN input. This is done with general-purpose routing so it's best to do it here to avoid conflicts. For this purpose, in the new bases, these special cells are of type IOBS (IOB Simplified). The proposed changes are compatible with bases of previous versions of Apycula and do not require changing .CST constraint files. Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
* clangformatgatecat2021-12-121-3/+3
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* gowin: BUGFIX. Place the ALU head in sliсe 0 onlyYRabbit2021-12-111-0/+3
| | | | Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
* gowin: Explicitly initialize the y in the clusterYRabbit2021-10-221-0/+5
| | | | Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
* gowin: Add ALU support.YRabbit2021-10-221-6/+211
| | | | | | | | - Both the mode used by yosys and all Gowin primitive modes are supported. - The ALU always starts with a zero slice. - The maximum length of the ALU chain is limited to one line of the chip. Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
* gowin: add support for wide LUTs.YRabbit2021-10-071-0/+261
| | | | | | | | | * A hardwired MUX within each logical cell is used. * The delay is equal 0. * No user placement constraints. * The output route contains dummy PIPs. They are ignored by gowin_pack, but it may be worth removing them. Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
* gowin: Add constraints on primitive placement.YRabbit2021-08-311-3/+13
| | | | | | | | | | Added support for the INS_LOC instruction in the constraints file (.CST), which is used to specify object placement. Expanded treatment of IO_LOC/IO_PORT constraints, which now can be applied to both ports and IO buffers. Port constraints have priority. Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
* gowin: Change the constraint parser to support multiple options per line. ↵YRabbit2021-08-061-1/+3
| | | | | | Add support for IOBUF and TBUF I/O modes. Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
* Fixing old emails and names in copyrightsgatecat2021-06-121-1/+1
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* Using hashlib in archesgatecat2021-06-021-5/+4
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* Use hashlib for core netlist structuresgatecat2021-06-021-11/+14
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* clangformatDavid Shah2020-12-301-13/+9
| | | | Signed-off-by: David Shah <dave@ds0.me>
* Gowin target (#542)Pepijn de Vos2020-12-301-0/+291
* load wires * add slice bels * add IOB * add aliases * local aliases * broken packing stuff * working packer * add constraints * pnr runs1111 * add timing info * constraints * more constraint stuff * add copyright * remove generic reference * remove parameters * remove generic python api * add newline to end of file * some small refactoring * warn on invalid constraints * don't error on missing cell * comment out debugging print * typo * avoid copy * faster empty idstring * remove intermediate variable * no more deadnames * fix cst warnings * increase ripup and epsilon a bit * take single device parameter * add info to readme * gui stubs * Revert 4d03b681a8634e978bd5af73c97665500047e055 * assign ff_used in assignArchInfo * decrease beta for better routability * try to fix CI
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