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* gowin: fix compilationYRabbit2022-07-191-8/+0
| | | | Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
* gowin: Remove incomprehensible names of the muxesYRabbit2022-07-197-34/+30
| | | | | | | | | | | | There is no need to multiply item names, it is a rudiment of my very first addition to nextpnr. Fully compatible with older versions of Apicula. Note: the cosmetic changes in lines with RAM are not my initiative, but the result of applying clang-format. Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
* gowin: Remove unnecessary functionsYRabbit2022-07-052-33/+9
| | | | Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
* Merge branch 'master' into clock-wipYRabbit2022-07-056-0/+187
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| * use DFF RAM modePepijn de Vos2022-07-021-1/+4
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| * Merge branch 'master' into shadowramPepijn de Vos2022-07-025-15/+310
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| * | hook up CE maybePepijn de Vos2022-06-163-0/+4
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| * | lutram actually PnRsPepijn de Vos2022-06-065-38/+43
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| * | WIP shadowramPepijn de Vos2022-06-056-0/+175
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* | | gowin: fix compilationYRabbit2022-07-041-0/+1
| | | | | | | | | | | | Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
* | | gowin: Let the placer know about global networksYRabbit2022-07-045-259/+367
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Refactor in order to detect networks that will be routed in a special mode earlier. This makes it possible to mark the source of such networks as a global buffer, thereby removing their influence on element placement. In addition, timing classes are set for some cells. Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
* | | gowin: process the CLK ports of the ODDR[C] primitivesYRabbit2022-06-242-7/+9
| | | | | | | | | | | | | | | | | | Also removed the useless references. Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
* | | gowin: add a separate router for the clocksYRabbit2022-06-235-1/+392
| |/ |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | A simple router that takes advantage of the fact that in each cell with DFFs their CLK inputs can directly connect to the global clock network. Networks with a large number of such sinks are sought and then each network is assigned to the available independent global clock networks. There are limited possibilities for routing mixed networks, that is, when the sinks are not only CLKs: in this case an attempt is made to use wires such as SN10/20 and EW10/20, that is, one short transition can be added between the global clock network and the sink. * At this time, networks with a source other than the I/O pin are not supported. This is typical for Tangnano4k and runber boards. * Router is disabled by default, you need to specify option --enable-globals to activate * No new chip bases are required. This may change in the distant future. Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
* | gowin: Use local aliasesYRabbit2022-06-091-7/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In the Gowin chips, the tiles are connected to each other by a one-hop wire, among others. There are 4 one-hop wires, of which 2 are shared between north/south and east/west, have three names: e.g. SN10 and N110 and S110. But only one of them, the first, occurs as a sink for PIP, that is, you can not get a route that would pass through the S110 for example. This commit corrects the names to SN?0 and EW?0 at the wire creation stage to avoid dead wires. In addition, the SN?0 and EW?0 are among the few sinks for global clock wires and now there is the possibility of a more optimal clock routing. Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
* | gowin: Add support for long wiresYRabbit2022-05-275-8/+299
|/ | | | | | | | | | | | | | | | | | | | | | Gowin chips have a highly sophisticated system of long wires that are wired to each cell and allow the clock or logic to spread quickly. This commit implements some of the capabilities of the long wire system for quadrants, leaving out the fine-tuning of them for each column. To make use of the long wire system, the specified wire is cut at the driver and a special cell is placed between the driver and the rest of the wire. * VCC and GND can not use long wires because they are in every cell and there is no point in using a net * Long wire numbers can be specified manually or assigned automatically. * The route from the driver to the port of the new cell can be quite long, this will have to be solved somehow. * It might make sense to add a mechanism for automatically finding candidates for long wires. Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
* gowin: Add initial syntax support for long wiresYRabbit2022-05-021-7/+27
| | | | | | | Only the recognition of the directive in the .CST file and elementary checks are added, but not the long-wire mechanism itself. Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
* gowin: handle the GW1N-9 feature.YRabbit2022-04-034-2/+40
| | | | | | | | This chip has a different default state for one type of I/O buffer --- you have to explicitly switch it to the normal state by feeding VCC/VSS to certain inputs. Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
* gowin: Fix z-index of oscillatorTim Pambor2022-03-302-5/+6
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* gowin: Add bels for oscillatorTim Pambor2022-03-272-0/+46
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* gowin: Consider the peculiarity of GW1BR-9CYRabbit2022-03-264-0/+27
| | | | | | | The GW1NR-9C chip ODDR implementation differs from all other supported chips by two suspicious inputs. Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
* gowin: Name the constants (#958)YRabbit2022-03-211-2/+2
| | | | | Place arbitrary constants side by side to avoid conflicts. Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
* Gowin: use global VCC and VSS nets (#956)Pepijn de Vos2022-03-194-10/+22
| | | | | | | * use global VCC and VSS nets * derp * remove init parameter
* gowin: don't crash if no arguments are setYRabbit2022-03-161-0/+4
| | | | Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
* Merge pull request #943 from yrabbit/localegatecat2022-03-151-0/+1
|\ | | | | gowin: support for locales other than en_US and C
| * Set the locale as early as possibleYRabbit2022-03-161-9/+0
| | | | | | | | Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
| * gowin: test locale workaroundYRabbit2022-03-151-1/+5
| | | | | | | | Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
| * gowin: support for locales other than en_US and CYRabbit2022-03-141-0/+6
| | | | | | | | | | | | | | Specifically, those locales where the fractional part separator in floating point numbers is not a dot. Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
* | gowin: add support for ODDR primitiveYRabbit2022-03-155-11/+177
|/ | | | | | | | | Compatible with older versions of apicula bases. Also small fixes and as the number of virtual Bels grows it is necessary to assign them Z coordinate in a centralized way to avoid conflicts and for this purpose introduced the BelZ enum. Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
* gowin: Add the Global Set/Reset primitiveYRabbit2022-03-124-0/+51
| | | | | | | | | GSR is added automatically if it was not instantiated by the user explicitly. Compatible with old apicula bases, the functionality does not work, but the crash does not happen --- just a warning. Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
* Merge pull request #931 from yrabbit/bugfix-0gatecat2022-03-041-0/+10
|\ | | | | gowin: BUGFIX gui crash
| * gowin: BUGFIX gui crashYRabbit2022-03-041-0/+10
| | | | | | | | Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
* | Switch to potentially-sparse net users arraygatecat2022-02-271-5/+6
| | | | | | | | | | | | | | | | This uses a new data structure for net.users that allows gaps, so removing a port from a net is no longer an O(n) operation on the number of users the net has. Signed-off-by: gatecat <gatecat@ds0.me>
* | gowin: recognize partnumbers of GW1NZ-1YRabbit2022-02-241-1/+1
|/ | | | | | | | | | | The model should be recognized by the partnumber, --family is needed only if the same partnumbers belong to different models. This is done in order to automatically generate parameters for calling nextpnr from Gowin files without problems: there also only partnumber is used and only in some cases the model is specified with the -name parameter and GW1NZ-1 is not such a case. Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
* gowin: Add support for true differential outputYRabbit2022-02-232-0/+87
| | | | | | | | | The new primitive appears as an amalgamation of two existing OBUF primitives. Compatible with older versions of apicula, although, of course, using TLVDS_OBUF with old databases will not bring the desired result, but no crash. Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
* Merge pull request #913 from chiplet/gw1nz-1gatecat2022-02-201-1/+1
|\ | | | | gowin: Add GW1NZ-1 support
| * gowin: Add GW1NZ-1Verneri Hirvonen2022-02-151-1/+1
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* | refactor: New member functions to replace design_utilsgatecat2022-02-183-55/+55
| | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me>
* | refactor: Use constids instead of id("..")gatecat2022-02-164-43/+52
| | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me>
* | refactor: Use cell member functions to add portsgatecat2022-02-161-20/+14
| | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me>
* | refactor: New NetInfo and CellInfo constructorsgatecat2022-02-162-11/+5
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* | clangformatgatecat2022-02-161-7/+7
|/ | | | Signed-off-by: gatecat <gatecat@ds0.me>
* add GW1N-9C dbPepijn de Vos2022-02-061-1/+1
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* gowin: add an option to manually specify familyIcenowy Zheng2022-02-061-6/+11
| | | | | | | | | | | In the vendor IDE, there's a device family named GW1N-9C (which seems to mean C revision of GW1N-9), in which the model numbers are all the same with GW1N-9. Add an option to nextpnr-gowin to allow manually specified family for this situation. Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
* Merge pull request #906 from yrabbit/gowin-gui-nocgatecat2022-02-041-4/+4
|\ | | | | gowin: Speed up the GUI
| * gowin: Speed up the GUIYRabbit2022-02-041-4/+4
| | | | | | | | | | | | By mistake, an empty decal gets filled with graphical elements. Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
* | gowin: Remove leftover debuggingYRabbit2022-02-041-1/+0
| | | | | | | | Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
* | Merge branch 'master' into diff-locationsYRabbit2022-02-048-17/+6527
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| * | run clangformatgatecat2022-02-031-1/+0
| |/ | | | | | | Signed-off-by: gatecat <gatecat@ds0.me>
| * gowin: Rearrange the GUI constantsYRabbit2022-02-032-4896/+4896
| | | | | | | | | | | | | | All internal constants for describing the graphics have been moved to the .cc file. Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
| * gowin: Add GUI.YRabbit2022-01-298-17/+6528
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * Items such as LUT, DFF, MUX, ALU, IOB are displayed; * Local wires, 1-2-4-8 wires are displayed; * The clock spines, taps and branches are displayed with some caveats. For now, you can not create a project in the GUI because of possible conflict with another PR (about GW1NR-9C support), but you can specify the board in the command line and load .JSON and .CST in the GUI. Although ALUs are displayed, but the CIN and COUT wires are not. This is still an unsolved problem. Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
generated by cgit v1.2.3 (git 2.25.1) at 2024-07-01 05:08:49 +0000