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* gowin: improve error messageYRabbit2023-01-191-1/+2
| | | | Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
* gowin: to use the FB network detection functionYRabbit2023-01-191-0/+6
| | | | | | | The chip used in tangnano4k does not have such pins, but we call the function anyway in the expectation of other chips. Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
* gowin: add a PLL primitive for the GW1NS-4 seriesYRabbit2023-01-187-38/+202
| | | | | | | | | | * both instances of the new PLLVR type are supported; * primitive placement is optimized for the use of dedicated PLL clock pins; * all 4 outputs of each primitive can use the clock nets (only 5 lines in total at the same time so far). Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
* gowin: improve clock wire routingYRabbit2022-12-305-45/+69
| | | | | | | | | | | | | | The dedicated router for clock wires now understands not only the IO pins but also the rPLL outputs as clock sources. This simple router sets an optimal route, so it is now the default router. It can be disabled with the --disable-globals command line flag if desired, but this is not recommended due to possible clock skew. Still for GW1N-4C there is no good router for clock wires as there external quartz resonator is connected via PLL. Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
* gowin: correct the delay calculationYRabbit2022-12-291-5/+16
| | | | | | | And do a full enumeration when searching for a delay because it is not yet clear whether the orderliness of the vector is guaranteed. Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
* gowin: fix build for wasmYRabbit2022-12-213-0/+12
| | | | | | | | A large number of global variables are not suitable for WASM, so completely disable the graphics part where the main array of them is used. For other architectures GUI is still possible. Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
* gowin: not crush on unknown clock tap's sourcesYRabbit2022-12-141-1/+1
| | | | | | As preparation for possible changes to the clock wiring system. Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
* gowin: BUGFIX: Correctly handle resetsYRabbit2022-12-092-13/+14
| | | | | | | | | | When a single primitive occupies several cells, care must be taken when manipulating the parameters of that primitive: when creating cells, each cell must receive a copy of all the parameters and not modify them unnecessarily. That is, if possible, it is better to make all parameter changes before dividing the primitive into cells. Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
* Merge pull request #1059 from YosysHQ/gatecat/validity-errorsmyrtle2022-12-072-2/+2
|\ | | | | Add new option for verbose validity errors, use for ice40
| * api: add explain_invalid option to isBelLocationValidgatecat2022-12-072-2/+2
| | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me>
* | Merge pull request #1058 from YosysHQ/gatecat/bounds-refactormyrtle2022-12-072-3/+3
|\| | | | | refactor: rename ArcBounds -> BoundingBox and use this in HeAP
| * refactor: ArcBounds -> BoundingBoxgatecat2022-12-072-3/+3
| | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me>
* | gowin: change the way networks are handledYRabbit2022-12-061-7/+8
| | | | | | | | | | | | | | Until a comprehensive clock router is developed, the order in which private cases are handled is important. Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
* | gowin: add PLL pins processingYRabbit2022-12-045-10/+133
|/ | | | | | | | | | | Uses the information of the special input pins for the PLL in the current chip. If such pins are involved, no routing is performed and information about the use of implicit wires is passed to the packer. The RESET and RESET_P inputs are now also disabled if they are connected to VSS/VCC. Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
* gowin: add information about pin configurationsYRabbit2022-11-252-4/+22
| | | | | | | Includes information on additional pin functions such as RPLL_C_IN, GCLKC_3, SCLK and others. This allows a decision to be made about special network routing of such pins Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
* gowin: mark the PLL ports that are not in useYRabbit2022-11-202-0/+16
| | | | | | | Unused ports are deactivated by special fuse combinations, rather than being left dangling in the air. Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
* gowin: add support for a more common chipYRabbit2022-11-121-1/+1
| | | | | | | | The GW1N-1 and GW1NZ-1 have a similar PLL, but the board with the former chip is already very hard to buy, so let's experiment with a more affordable chip. Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
* gowin: use ctx->idf() a bitYRabbit2022-11-112-41/+17
| | | | | | | Replacing snprintf() with ctx->idf() in PLL commit, but not yet a complete overhaul. Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
* gowin: add initial PLL supportYRabbit2022-11-106-1/+227
| | | | | | | | | | | The rPLL primitive for the simplest chip (GW1N-1) in the family is processed. All parameters of the primitive are passed on to gowin_pack, and general-purpose wires are used for routing outputs of the primitive. Compatible with older versions of apicula, but in this case will refuse to place the new primitive. Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
* run clangformatgatecat2022-10-171-1/+2
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* support windows line endingsLushay Labs2022-10-091-4/+4
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* gowin: BUGFIX. Really memorize the chipYRabbit2022-08-251-0/+2
| | | | | | | When it really needed to distinguish between the chips, this unforgivable error was discovered :) Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
* refactor: Use IdString::in instead of || chainsgatecat2022-08-103-6/+4
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* refactor: id(stringf(...)) to new idf(...) helpergatecat2022-08-101-1/+1
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* gowin: fix compilationYRabbit2022-07-191-8/+0
| | | | Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
* gowin: Remove incomprehensible names of the muxesYRabbit2022-07-197-34/+30
| | | | | | | | | | | | There is no need to multiply item names, it is a rudiment of my very first addition to nextpnr. Fully compatible with older versions of Apicula. Note: the cosmetic changes in lines with RAM are not my initiative, but the result of applying clang-format. Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
* gowin: Remove unnecessary functionsYRabbit2022-07-052-33/+9
| | | | Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
* Merge branch 'master' into clock-wipYRabbit2022-07-056-0/+187
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| * use DFF RAM modePepijn de Vos2022-07-021-1/+4
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| * Merge branch 'master' into shadowramPepijn de Vos2022-07-025-15/+310
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| * | hook up CE maybePepijn de Vos2022-06-163-0/+4
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| * | lutram actually PnRsPepijn de Vos2022-06-065-38/+43
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| * | WIP shadowramPepijn de Vos2022-06-056-0/+175
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* | | gowin: fix compilationYRabbit2022-07-041-0/+1
| | | | | | | | | | | | Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
* | | gowin: Let the placer know about global networksYRabbit2022-07-045-259/+367
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Refactor in order to detect networks that will be routed in a special mode earlier. This makes it possible to mark the source of such networks as a global buffer, thereby removing their influence on element placement. In addition, timing classes are set for some cells. Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
* | | gowin: process the CLK ports of the ODDR[C] primitivesYRabbit2022-06-242-7/+9
| | | | | | | | | | | | | | | | | | Also removed the useless references. Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
* | | gowin: add a separate router for the clocksYRabbit2022-06-235-1/+392
| |/ |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | A simple router that takes advantage of the fact that in each cell with DFFs their CLK inputs can directly connect to the global clock network. Networks with a large number of such sinks are sought and then each network is assigned to the available independent global clock networks. There are limited possibilities for routing mixed networks, that is, when the sinks are not only CLKs: in this case an attempt is made to use wires such as SN10/20 and EW10/20, that is, one short transition can be added between the global clock network and the sink. * At this time, networks with a source other than the I/O pin are not supported. This is typical for Tangnano4k and runber boards. * Router is disabled by default, you need to specify option --enable-globals to activate * No new chip bases are required. This may change in the distant future. Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
* | gowin: Use local aliasesYRabbit2022-06-091-7/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In the Gowin chips, the tiles are connected to each other by a one-hop wire, among others. There are 4 one-hop wires, of which 2 are shared between north/south and east/west, have three names: e.g. SN10 and N110 and S110. But only one of them, the first, occurs as a sink for PIP, that is, you can not get a route that would pass through the S110 for example. This commit corrects the names to SN?0 and EW?0 at the wire creation stage to avoid dead wires. In addition, the SN?0 and EW?0 are among the few sinks for global clock wires and now there is the possibility of a more optimal clock routing. Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
* | gowin: Add support for long wiresYRabbit2022-05-275-8/+299
|/ | | | | | | | | | | | | | | | | | | | | | Gowin chips have a highly sophisticated system of long wires that are wired to each cell and allow the clock or logic to spread quickly. This commit implements some of the capabilities of the long wire system for quadrants, leaving out the fine-tuning of them for each column. To make use of the long wire system, the specified wire is cut at the driver and a special cell is placed between the driver and the rest of the wire. * VCC and GND can not use long wires because they are in every cell and there is no point in using a net * Long wire numbers can be specified manually or assigned automatically. * The route from the driver to the port of the new cell can be quite long, this will have to be solved somehow. * It might make sense to add a mechanism for automatically finding candidates for long wires. Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
* gowin: Add initial syntax support for long wiresYRabbit2022-05-021-7/+27
| | | | | | | Only the recognition of the directive in the .CST file and elementary checks are added, but not the long-wire mechanism itself. Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
* gowin: handle the GW1N-9 feature.YRabbit2022-04-034-2/+40
| | | | | | | | This chip has a different default state for one type of I/O buffer --- you have to explicitly switch it to the normal state by feeding VCC/VSS to certain inputs. Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
* gowin: Fix z-index of oscillatorTim Pambor2022-03-302-5/+6
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* gowin: Add bels for oscillatorTim Pambor2022-03-272-0/+46
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* gowin: Consider the peculiarity of GW1BR-9CYRabbit2022-03-264-0/+27
| | | | | | | The GW1NR-9C chip ODDR implementation differs from all other supported chips by two suspicious inputs. Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
* gowin: Name the constants (#958)YRabbit2022-03-211-2/+2
| | | | | Place arbitrary constants side by side to avoid conflicts. Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
* Gowin: use global VCC and VSS nets (#956)Pepijn de Vos2022-03-194-10/+22
| | | | | | | * use global VCC and VSS nets * derp * remove init parameter
* gowin: don't crash if no arguments are setYRabbit2022-03-161-0/+4
| | | | Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
* Merge pull request #943 from yrabbit/localegatecat2022-03-151-0/+1
|\ | | | | gowin: support for locales other than en_US and C
| * Set the locale as early as possibleYRabbit2022-03-161-9/+0
| | | | | | | | Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
| * gowin: test locale workaroundYRabbit2022-03-151-1/+5
| | | | | | | | Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
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