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| * Use settings for placer1 and router1Miodrag Milanovic2018-08-091-2/+0
* | Improve iCE40 gfx for IO tiles and RAM tilesClifford Wolf2018-08-181-0/+2
* | Add ice40 wire attributes (grid position, segment list)Clifford Wolf2018-08-181-18/+5
* | Add Arch attrs APIClifford Wolf2018-08-141-0/+18
* | Merge remote-tracking branch 'origin/master' into placer_speedupEddie Hung2018-08-101-1/+11
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| * Add pip locationsClifford Wolf2018-08-091-1/+11
* | Rework Arch::logicCellsCompatible() to take pointer + size, allowing use of s...Eddie Hung2018-08-101-1/+1
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* Merge branch 'master' of github.com:YosysHQ/nextpnr into constidsClifford Wolf2018-08-081-10/+11
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| * Merge pull request #44 from YosysHQ/improve_timing_specDavid Shah2018-08-081-10/+10
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| | * Arch API: Removing Arch::isIOCellDavid Shah2018-08-081-2/+0
| | * Arch API: New specification for timing port classesDavid Shah2018-08-081-4/+2
| | * clangformatEddie Hung2018-08-061-6/+8
| | * Add new Arch::isIOCell() API functionEddie Hung2018-08-061-0/+2
| | * Change getBudgetOverride() signature to return bool and modify budget in placeEddie Hung2018-08-051-1/+1
| * | Merge remote-tracking branch 'origin/master' into common_mainMiodrag Milanovic2018-08-081-47/+46
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| * | | Added project loaderMiodrag Milanovic2018-08-061-0/+1
* | | | Get rid of old iCE40 id_ Arch membersClifford Wolf2018-08-081-10/+1
* | | | Get rid of PortPin and BelType (ice40, generic, docs)Clifford Wolf2018-08-081-19/+13
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* | | Change getBudgetOverride() signature to return bool and modify budget in placeEddie Hung2018-08-061-1/+1
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* | API change: Use CellInfo* and NetInfo* as cell/net handles (common, ice40)Clifford Wolf2018-08-051-46/+45
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* clangformatClifford Wolf2018-08-051-12/+12
* Add new iCE40 delay estimator and delay predictorClifford Wolf2018-08-041-2/+1
* Refactor ice40 timing fuzzer used to create delay estimatesClifford Wolf2018-08-041-0/+2
* Merge branch 'master' of github.com:YosysHQ/nextpnr into lutpermClifford Wolf2018-08-041-0/+2
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| * clangformatDavid Shah2018-08-041-1/+0
| * Add constraint weight as a command line optionDavid Shah2018-08-031-0/+3
* | Proper ice40 wire typesClifford Wolf2018-08-031-1/+20
* | Add iCE40 pseudo-pips for lut permutationClifford Wolf2018-08-031-8/+30
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* Merge pull request #22 from YosysHQ/routethruClifford Wolf2018-08-031-1/+11
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| * Add LUT route-through pips to iCE40 architecture databaseClifford Wolf2018-08-021-1/+11
* | ice40: Use real cell timingsDavid Shah2018-08-021-1/+1
* | ice40: Adding cell timings to chipdbDavid Shah2018-08-021-0/+15
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* Remove getFrameDecal() APIClifford Wolf2018-08-011-1/+0
* Merge branch 'redist_slack' into 'master'David Shah2018-08-011-0/+2
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| * Modify the getNetinfo*() functions and getBudgetOverride() to not useEddie Hung2018-07-311-1/+1
| * Merge remote-tracking branch 'origin/estdelay' into redist_slackEddie Hung2018-07-311-0/+1
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| | * Modify predictDelay signatureEddie Hung2018-07-301-1/+1
| | * Add predictDelay Arch APIClifford Wolf2018-07-301-0/+1
| * | Merge branch 'redist_slack' into 'redist_slack'Eddie Hung2018-07-311-0/+1
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| | * | getBudgetOverride() now handles COUT crossing tilesEddie Hung2018-07-261-1/+1
| | * | Revert "Remove Arch::getBudgetOverride()"Eddie Hung2018-07-261-0/+1
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* | / clangformatSergiusz Bazanski2018-08-011-2/+2
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* | getChipName() should be constClifford Wolf2018-07-311-1/+1
* | Add binary search to getBelPinWire() and getBelPinType()Clifford Wolf2018-07-311-1/+1
* | Use DelayInfo for cell timing instead of delay_tDavid Shah2018-07-301-1/+1
* | Add iCE40 fast/slow delay fields to chipdbClifford Wolf2018-07-301-2/+15
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* Add getWireType()/getPipType() APIClifford Wolf2018-07-261-0/+4
* Merge remote-tracking branch 'origin/master' into eddieh/idstring_speedupEddie Hung2018-07-251-0/+12
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| * ice40: after reviewSergiusz Bazanski2018-07-251-1/+1
| * ice40: support PLL40_*_PAD, fix pass-through LUT for LOCKSergiusz Bazanski2018-07-251-0/+12
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