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* timing: Path related fixesDavid Shah2019-01-271-1/+4
* ice40: Add helper to know which global network is driven by a SB_GB BelSylvain Munaut2018-11-261-0/+7
* ice40: Add GlobalNetowkrInfo in the chip databaseSylvain Munaut2018-11-191-1/+17
* ice40/arch: Add helper to check if a BEL is LOCKED or notSylvain Munaut2018-11-191-0/+2
* Merge remote-tracking branch 'origin/master' into timingapiEddie Hung2018-11-131-0/+1
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| * [ice40] getBudgetOverride() to use constrained Z not placed ZEddie Hung2018-11-131-0/+1
* | Merge remote-tracking branch 'origin/master' into timingapiEddie Hung2018-11-131-17/+37
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| * Merge pull request #107 from YosysHQ/router_improveEddie Hung2018-11-131-17/+37
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| | * clangformatClifford Wolf2018-11-111-4/+1
| | * Add getConflictingWireWire() arch API, streamline getConflictingXY semanticClifford Wolf2018-11-111-14/+29
| | * Add getConflictingPipWire() arch API, router1 improvementsClifford Wolf2018-11-111-9/+17
* | | archapi: Add getDelayFromNS to improve timing algorithm portabilityDavid Shah2018-11-121-0/+6
* | | timing: iCE40 Arch API changes for clocking infoDavid Shah2018-11-121-2/+4
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* / fix grid dimensions for ice40Miodrag Milanovic2018-10-271-2/+2
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* clangformatDavid Shah2018-09-301-1/+1
* Add iCE40 gfx for span-4 wires between IO tilesClifford Wolf2018-08-191-2/+0
* Merge pull request #47 from YosysHQ/settings_propagateClifford Wolf2018-08-181-2/+0
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| * Use settings for placer1 and router1Miodrag Milanovic2018-08-091-2/+0
* | Improve iCE40 gfx for IO tiles and RAM tilesClifford Wolf2018-08-181-0/+2
* | Add ice40 wire attributes (grid position, segment list)Clifford Wolf2018-08-181-18/+5
* | Add Arch attrs APIClifford Wolf2018-08-141-0/+18
* | Merge remote-tracking branch 'origin/master' into placer_speedupEddie Hung2018-08-101-1/+11
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| * Add pip locationsClifford Wolf2018-08-091-1/+11
* | Rework Arch::logicCellsCompatible() to take pointer + size, allowing use of s...Eddie Hung2018-08-101-1/+1
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* Merge branch 'master' of github.com:YosysHQ/nextpnr into constidsClifford Wolf2018-08-081-10/+11
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| * Merge pull request #44 from YosysHQ/improve_timing_specDavid Shah2018-08-081-10/+10
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| | * Arch API: Removing Arch::isIOCellDavid Shah2018-08-081-2/+0
| | * Arch API: New specification for timing port classesDavid Shah2018-08-081-4/+2
| | * clangformatEddie Hung2018-08-061-6/+8
| | * Add new Arch::isIOCell() API functionEddie Hung2018-08-061-0/+2
| | * Change getBudgetOverride() signature to return bool and modify budget in placeEddie Hung2018-08-051-1/+1
| * | Merge remote-tracking branch 'origin/master' into common_mainMiodrag Milanovic2018-08-081-47/+46
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| * | | Added project loaderMiodrag Milanovic2018-08-061-0/+1
* | | | Get rid of old iCE40 id_ Arch membersClifford Wolf2018-08-081-10/+1
* | | | Get rid of PortPin and BelType (ice40, generic, docs)Clifford Wolf2018-08-081-19/+13
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* | | Change getBudgetOverride() signature to return bool and modify budget in placeEddie Hung2018-08-061-1/+1
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* | API change: Use CellInfo* and NetInfo* as cell/net handles (common, ice40)Clifford Wolf2018-08-051-46/+45
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* clangformatClifford Wolf2018-08-051-12/+12
* Add new iCE40 delay estimator and delay predictorClifford Wolf2018-08-041-2/+1
* Refactor ice40 timing fuzzer used to create delay estimatesClifford Wolf2018-08-041-0/+2
* Merge branch 'master' of github.com:YosysHQ/nextpnr into lutpermClifford Wolf2018-08-041-0/+2
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| * clangformatDavid Shah2018-08-041-1/+0
| * Add constraint weight as a command line optionDavid Shah2018-08-031-0/+3
* | Proper ice40 wire typesClifford Wolf2018-08-031-1/+20
* | Add iCE40 pseudo-pips for lut permutationClifford Wolf2018-08-031-8/+30
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* Merge pull request #22 from YosysHQ/routethruClifford Wolf2018-08-031-1/+11
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| * Add LUT route-through pips to iCE40 architecture databaseClifford Wolf2018-08-021-1/+11
* | ice40: Use real cell timingsDavid Shah2018-08-021-1/+1
* | ice40: Adding cell timings to chipdbDavid Shah2018-08-021-0/+15
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* Remove getFrameDecal() APIClifford Wolf2018-08-011-1/+0
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