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* clangformatEddie Hung2018-07-251-3/+2
* ice40: fixes before reviewSergiusz Bazanski2018-07-241-6/+6
* ice40: move PLL->IO from pseudo pip to second uphill belSergiusz Bazanski2018-07-241-15/+16
* ice40: emit list of upbels in chipdbSergiusz Bazanski2018-07-241-1/+1
* clang-formatSergiusz Bazanski2018-07-241-14/+21
* ice40: A slightly nicer way to do this.Sergiusz Bazanski2018-07-241-46/+31
* ice40: Refactor PLL/LOCK LUT splicing out into Arch::Sergiusz Bazanski2018-07-241-0/+1
* ice40: Implement emitting PLLsSergiusz Bazanski2018-07-241-14/+104
* clangformatDavid Shah2018-07-231-2/+3
* Move to new API and remove deprecatedMiodrag Milanovic2018-07-221-36/+38
* Rename getWireBelPin to getBelPinWireClifford Wolf2018-07-221-3/+3
* Added driver and users for netsMiodrag Milanovic2018-07-211-0/+8
* Map ports to netsMiodrag Milanovic2018-07-211-0/+14
* create io cells out of ascMiodrag Milanovic2018-07-211-0/+27
* add cells that are in default state or no configurationMiodrag Milanovic2018-07-211-0/+40
* Add used cells and attach them to belsMiodrag Milanovic2018-07-211-0/+39
* Assign proper pipsMiodrag Milanovic2018-07-211-9/+27
* add only missing netMiodrag Milanovic2018-07-211-3/+6
* fix introduced bugMiodrag Milanovic2018-07-211-0/+2
* Bind wires to netMiodrag Milanovic2018-07-201-629/+637
* Few more checks on parameters and error eolMiodrag Milanovic2018-07-201-4/+4
* Start adding bitstream reading for ice40Miodrag Milanovic2018-07-201-33/+133
* ice40: Packer and bitstream gen support for MAC16sDavid Shah2018-07-191-1/+89
* Reducing performance cost of assertsDavid Shah2018-07-191-1/+1
* ice40: Fixes for inverted clocksDavid Shah2018-07-181-1/+1
* ice40: Assign ArchArgs after packingDavid Shah2018-07-181-2/+3
* Revert "Make ice40::Arch thread-safe"Sergiusz Bazanski2018-07-141-5/+5
* Revert "Remove legacy access to state via Arch"Sergiusz Bazanski2018-07-141-7/+6
* Remove legacy access to state via ArchSergiusz Bazanski2018-07-141-6/+7
* Make ice40::Arch thread-safeSergiusz Bazanski2018-07-131-5/+5
* Updates from clang-formatClifford Wolf2018-07-121-3/+2
* Add NPNR_ASSERT_FALSE, use in bitstream.ccDavid Shah2018-07-041-2/+2
* refactor: Replace assert with NPNR_ASSERTDavid Shah2018-07-041-11/+11
* Fixed macros and includes for MSVCMiodrag Milanovic2018-07-031-0/+1
* ice40: UltraPlus SPRAM workingDavid Shah2018-06-291-0/+23
* ice40: PLace legaliser produces a design that is at least routable for picosocDavid Shah2018-06-281-1/+2
* CarryInSet added to bitstream gen, add counter tbDavid Shah2018-06-261-0/+7
* Working on debugging carry packerDavid Shah2018-06-261-2/+2
* nets and cells are unique_ptr'sMiodrag Milanovic2018-06-251-17/+17
* Update from increased clangformat line lengthDavid Shah2018-06-231-126/+62
* Refactoring bind/unbind APIClifford Wolf2018-06-231-1/+1
* ice40: Fix UltraPlus quasi-logic-cell bitsDavid Shah2018-06-231-25/+29
* Cleanup almost all deprecation warningsMiodrag Milanovic2018-06-231-2/+2
* ice40: SB_LFOSC support, fabric routing onlyDavid Shah2018-06-221-8/+33
* ice40: Adding extra cell wires to database; SB_WARMBOOT workingDavid Shah2018-06-221-1/+2
* ice40: Add UltraPlus tiles to databaseDavid Shah2018-06-221-0/+15
* Switched from clifford@clifford.at to clifford@symbioticeda.com for copyright...Clifford Wolf2018-06-221-1/+1
* Fixing 5k bitstream gen and place heuristicsDavid Shah2018-06-221-1/+12
* Getting rid of old IdString API users, Add ctx to many internal APIsClifford Wolf2018-06-181-24/+30
* Rename Design to Context, derive from Arch instead of instantiatingClifford Wolf2018-06-181-35/+34
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