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* ice40: Add PCF support for -pullup, -pullup_resistor and -nowarnDavid Shah2018-12-201-2/+15
* ice40: Improve bitstream error handlingDavid Shah2018-12-061-2/+10
* clangformatDavid Shah2018-12-061-1/+1
* ice40: Add support for placing SB_LEDDA_IP block.Daniel Serpell2018-12-011-1/+2
* ice40: Update the way LVDS inputs are handled during bitstream generationSylvain Munaut2018-11-281-48/+48
* ice40: Add support for SB_RGBA_DRVSylvain Munaut2018-11-191-0/+5
* ice40: Add support for SB_GB_IOSylvain Munaut2018-11-191-0/+1
* ice40: Add support for PLL global outputs via PADINSylvain Munaut2018-11-191-44/+50
* ice40: Introduce the concept of forPadIn SB_GBSylvain Munaut2018-11-191-1/+17
* ice40/bitstream: Handle IoCtrl.IE_ polarity when configuring unused SB_IOSylvain Munaut2018-11-191-2/+7
* ice40/bitstream: Convert to UNIX line endingsSylvain Munaut2018-11-161-1043/+1043
* ice40: Remove unnecessary RAM assertionDavid Shah2018-11-161-1/+0
* ice40: Don't set colbuf bits for 384David Shah2018-11-111-0/+2
* clangformatDavid Shah2018-09-301-4/+1
* ice40: LVDS input bitstream supportDavid Shah2018-09-241-4/+48
* do not break if there are no nets loaded from sym sectionMiodrag Milanovic2018-08-181-4/+6
* Get rid of PortPin and BelType (ice40, generic, docs)Clifford Wolf2018-08-081-17/+17
* API change: Use CellInfo* and NetInfo* as cell/net handles (common, ice40)Clifford Wolf2018-08-051-24/+24
* clangformatClifford Wolf2018-08-051-21/+22
* ice40: Bitstream gen for LUT permutationDavid Shah2018-08-041-8/+78
* ice40: Add bitstream gen for routethru LUTsDavid Shah2018-08-031-9/+58
* ice40: Add HFOSC support, force fabric routing on oscillators for nowDavid Shah2018-08-011-0/+4
* clangformatSergiusz Bazanski2018-08-011-2/+3
* clangformatEddie Hung2018-07-251-3/+2
* ice40: fixes before reviewSergiusz Bazanski2018-07-241-6/+6
* ice40: move PLL->IO from pseudo pip to second uphill belSergiusz Bazanski2018-07-241-15/+16
* ice40: emit list of upbels in chipdbSergiusz Bazanski2018-07-241-1/+1
* clang-formatSergiusz Bazanski2018-07-241-14/+21
* ice40: A slightly nicer way to do this.Sergiusz Bazanski2018-07-241-46/+31
* ice40: Refactor PLL/LOCK LUT splicing out into Arch::Sergiusz Bazanski2018-07-241-0/+1
* ice40: Implement emitting PLLsSergiusz Bazanski2018-07-241-14/+104
* clangformatDavid Shah2018-07-231-2/+3
* Move to new API and remove deprecatedMiodrag Milanovic2018-07-221-36/+38
* Rename getWireBelPin to getBelPinWireClifford Wolf2018-07-221-3/+3
* Added driver and users for netsMiodrag Milanovic2018-07-211-0/+8
* Map ports to netsMiodrag Milanovic2018-07-211-0/+14
* create io cells out of ascMiodrag Milanovic2018-07-211-0/+27
* add cells that are in default state or no configurationMiodrag Milanovic2018-07-211-0/+40
* Add used cells and attach them to belsMiodrag Milanovic2018-07-211-0/+39
* Assign proper pipsMiodrag Milanovic2018-07-211-9/+27
* add only missing netMiodrag Milanovic2018-07-211-3/+6
* fix introduced bugMiodrag Milanovic2018-07-211-0/+2
* Bind wires to netMiodrag Milanovic2018-07-201-629/+637
* Few more checks on parameters and error eolMiodrag Milanovic2018-07-201-4/+4
* Start adding bitstream reading for ice40Miodrag Milanovic2018-07-201-33/+133
* ice40: Packer and bitstream gen support for MAC16sDavid Shah2018-07-191-1/+89
* Reducing performance cost of assertsDavid Shah2018-07-191-1/+1
* ice40: Fixes for inverted clocksDavid Shah2018-07-181-1/+1
* ice40: Assign ArchArgs after packingDavid Shah2018-07-181-2/+3
* Revert "Make ice40::Arch thread-safe"Sergiusz Bazanski2018-07-141-5/+5
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