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* ice40: Assign ArchArgs after packingDavid Shah2018-07-181-2/+3
* Revert "Make ice40::Arch thread-safe"Sergiusz Bazanski2018-07-141-5/+5
* Revert "Remove legacy access to state via Arch"Sergiusz Bazanski2018-07-141-7/+6
* Remove legacy access to state via ArchSergiusz Bazanski2018-07-141-6/+7
* Make ice40::Arch thread-safeSergiusz Bazanski2018-07-131-5/+5
* Updates from clang-formatClifford Wolf2018-07-121-3/+2
* Add NPNR_ASSERT_FALSE, use in bitstream.ccDavid Shah2018-07-041-2/+2
* refactor: Replace assert with NPNR_ASSERTDavid Shah2018-07-041-11/+11
* Fixed macros and includes for MSVCMiodrag Milanovic2018-07-031-0/+1
* ice40: UltraPlus SPRAM workingDavid Shah2018-06-291-0/+23
* ice40: PLace legaliser produces a design that is at least routable for picosocDavid Shah2018-06-281-1/+2
* CarryInSet added to bitstream gen, add counter tbDavid Shah2018-06-261-0/+7
* Working on debugging carry packerDavid Shah2018-06-261-2/+2
* nets and cells are unique_ptr'sMiodrag Milanovic2018-06-251-17/+17
* Update from increased clangformat line lengthDavid Shah2018-06-231-126/+62
* Refactoring bind/unbind APIClifford Wolf2018-06-231-1/+1
* ice40: Fix UltraPlus quasi-logic-cell bitsDavid Shah2018-06-231-25/+29
* Cleanup almost all deprecation warningsMiodrag Milanovic2018-06-231-2/+2
* ice40: SB_LFOSC support, fabric routing onlyDavid Shah2018-06-221-8/+33
* ice40: Adding extra cell wires to database; SB_WARMBOOT workingDavid Shah2018-06-221-1/+2
* ice40: Add UltraPlus tiles to databaseDavid Shah2018-06-221-0/+15
* Switched from clifford@clifford.at to clifford@symbioticeda.com for copyright...Clifford Wolf2018-06-221-1/+1
* Fixing 5k bitstream gen and place heuristicsDavid Shah2018-06-221-1/+12
* Getting rid of old IdString API users, Add ctx to many internal APIsClifford Wolf2018-06-181-24/+30
* Rename Design to Context, derive from Arch instead of instantiatingClifford Wolf2018-06-181-35/+34
* Rename Chip to Arch and ChipArgs to ArchArgsClifford Wolf2018-06-181-21/+21
* Merge branch 'master' of gitlab.com:SymbioticEDA/nextpnr into chipdbngClifford Wolf2018-06-171-1/+8
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| * ice40: Fixing negative clock bitstream generationDavid Shah2018-06-171-1/+8
* | Move top-level ChipInfoPOD into ice40 chipdb blobClifford Wolf2018-06-171-2/+2
* | Move BitstreamInfoPOD to ice40 chipdb blobClifford Wolf2018-06-171-5/+5
* | Merge branch 'master' of gitlab.com:SymbioticEDA/nextpnr into chipdbngClifford Wolf2018-06-171-7/+9
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| * General reformattingDavid Shah2018-06-171-1/+1
| * ice40: Add symbol output to bitstream generationDavid Shah2018-06-171-6/+8
| * Updating copyrightsDavid Shah2018-06-171-1/+1
* | Minor refactoring of BinaryBlobAssembler, fix alignmentsClifford Wolf2018-06-171-1/+1
* | Progress with chipdb refactoringClifford Wolf2018-06-161-1/+1
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* Update clangformatClifford Wolf2018-06-161-1/+1
* ice40: Fix BRAM initialisationDavid Shah2018-06-161-2/+3
* ice40: Include RAM init data in bitstreamDavid Shah2018-06-161-0/+40
* ice40: Fix bitstream generation when parameters are unspecifiedDavid Shah2018-06-161-13/+23
* ice40: Bitstream generation for RAMDavid Shah2018-06-161-1/+36
* Add nextpnr namespaceClifford Wolf2018-06-121-0/+4
* Remove pool, dict, vector namespace aliasesClifford Wolf2018-06-111-3/+4
* Improving 5k supportDavid Shah2018-06-101-14/+35
* Add support for iCE40 global buffers (currently only for 1k devices)Clifford Wolf2018-06-101-3/+28
* Debugging on icebreakerDavid Shah2018-06-101-9/+19
* ice40: Set config bits for unused IODavid Shah2018-06-101-1/+19
* ice40: Add IO config to bitstreamDavid Shah2018-06-101-12/+64
* ice40: Write logic cell config to bitstreamDavid Shah2018-06-101-5/+58
* ice40: Start adding routing to asc outputDavid Shah2018-06-101-0/+34
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