Commit message (Collapse) | Author | Age | Files | Lines | |
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* | Merge remote-tracking branch 'origin/master' into timingapi | Eddie Hung | 2018-11-13 | 2 | -4/+5 |
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| * | [ice40] getBudgetOverride() to use constrained Z not placed Z | Eddie Hung | 2018-11-13 | 2 | -4/+5 |
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* | | Merge remote-tracking branch 'origin/master' into timingapi | Eddie Hung | 2018-11-13 | 3 | -18/+41 |
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| * | Merge pull request #107 from YosysHQ/router_improve | Eddie Hung | 2018-11-13 | 2 | -17/+40 |
| |\ | | | | | | | Major rewrite of "router1" | ||||
| | * | Various router1 fixes, Add BelId/WireId/PipId::operator<() | Clifford Wolf | 2018-11-13 | 1 | -0/+3 |
| | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
| | * | clangformat | Clifford Wolf | 2018-11-11 | 1 | -4/+1 |
| | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
| | * | Add getConflictingWireWire() arch API, streamline getConflictingXY semantic | Clifford Wolf | 2018-11-11 | 1 | -14/+29 |
| | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
| | * | Add getConflictingPipWire() arch API, router1 improvements | Clifford Wolf | 2018-11-11 | 1 | -9/+17 |
| | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
| * | | Mark getArchOptions as override in derived classes | Pedro Vanzella | 2018-11-13 | 1 | -1/+1 |
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* | | | timing: Add support for clock constraints | David Shah | 2018-11-12 | 2 | -0/+12 |
| | | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me> | ||||
* | | | archapi: Add getDelayFromNS to improve timing algorithm portability | David Shah | 2018-11-12 | 1 | -0/+6 |
| | | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me> | ||||
* | | | timing: Fix handling of clock inputs | David Shah | 2018-11-12 | 1 | -2/+2 |
| | | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me> | ||||
* | | | Working on multi-clock analysis | David Shah | 2018-11-12 | 1 | -6/+4 |
| | | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me> | ||||
* | | | timing: iCE40 Arch API changes for clocking info | David Shah | 2018-11-12 | 3 | -21/+68 |
|/ / | | | | | | | Signed-off-by: David Shah <dave@ds0.me> | ||||
* | | ice40: Don't set colbuf bits for 384 | David Shah | 2018-11-11 | 1 | -0/+2 |
| | | | | | | | | Signed-off-by: David Shah <davey1576@gmail.com> | ||||
* | | Merge pull request #93 from YosysHQ/gui_changes | Miodrag Milanović | 2018-11-10 | 1 | -2/+2 |
|\ \ | |/ |/| | Gui changes | ||||
| * | fix grid dimensions for ice40 | Miodrag Milanovic | 2018-10-27 | 1 | -2/+2 |
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* | | ice40: Fix SPRAM and IO globals | David Shah | 2018-11-04 | 1 | -0/+4 |
| | | | | | | | | Signed-off-by: David Shah <dave@ds0.me> | ||||
* | | ice40: Fix PLL DYNAMICDELAY | David Shah | 2018-10-27 | 1 | -1/+2 |
|/ | | | | Signed-off-by: David Shah <davey1576@gmail.com> | ||||
* | ups, uncomment | Miodrag Milanovic | 2018-10-27 | 1 | -2/+2 |
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* | Fixed pip graphics | Miodrag Milanovic | 2018-10-27 | 1 | -4/+4 |
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* | Merge pull request #88 from YosysHQ/issue72 | Eddie Hung | 2018-10-11 | 1 | -6/+13 |
|\ | | | | | Resolve issue #72 | ||||
| * | [ice40] TimingPortClass of LC.O ports without any inputs now TMG_IGNORE | Eddie Hung | 2018-09-15 | 1 | -6/+13 |
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* | | Add info message for promoted global nets | Clifford Wolf | 2018-10-03 | 1 | -0/+2 |
| | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
* | | ice40: Add error for bad PACKAGE_PIN connections | David Shah | 2018-10-03 | 1 | -2/+13 |
| | | | | | | | | Signed-off-by: David Shah <davey1576@gmail.com> | ||||
* | | Refactor chain finder to its own file | David Shah | 2018-09-30 | 1 | -39/+1 |
| | | | | | | | | Signed-off-by: David Shah <davey1576@gmail.com> | ||||
* | | clangformat | David Shah | 2018-09-30 | 8 | -28/+34 |
| | | | | | | | | Signed-off-by: David Shah <davey1576@gmail.com> | ||||
* | | Merge pull request #79 from YosysHQ/ice40lvds | Clifford Wolf | 2018-09-25 | 8 | -13/+88 |
|\ \ | | | | | | | ice40: Adding LVDS input support | ||||
| * | | ice40: LVDS input bitstream support | David Shah | 2018-09-24 | 1 | -4/+48 |
| | | | | | | | | | | | | Signed-off-by: David Shah <davey1576@gmail.com> | ||||
| * | | ice40: Tristate IO support fixes | David Shah | 2018-09-24 | 3 | -6/+10 |
| | | | | | | | | | | | | Signed-off-by: David Shah <davey1576@gmail.com> | ||||
| * | | ice40: Validity check for LVDS IO | David Shah | 2018-09-24 | 4 | -0/+29 |
| | | | | | | | | | | | | Signed-off-by: David Shah <davey1576@gmail.com> | ||||
| * | | ice40: Remove obsolete belType member | David Shah | 2018-09-24 | 3 | -3/+1 |
| |/ | | | | | | | Signed-off-by: David Shah <davey1576@gmail.com> | ||||
* | | Merge pull request #76 from YosysHQ/plloutglobal_fix | Clifford Wolf | 2018-09-25 | 2 | -2/+38 |
|\ \ | | | | | | | Add needed PLLOUTGLOBAL ports and mapped it | ||||
| * | | Added required checks for PLL and fixed messages eol | Miodrag Milanovic | 2018-09-19 | 1 | -3/+31 |
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| * | | Add needed PLLOUTGLOBAL ports and mapped it properly | Miodrag Milanovic | 2018-09-12 | 2 | -0/+8 |
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* / | ice40: Fix carry packer bug | David Shah | 2018-09-25 | 1 | -2/+2 |
|/ | | | | Signed-off-by: David Shah <davey1576@gmail.com> | ||||
* | Merge pull request #56 from YosysHQ/q3k/issue-55 | Serge Bazanski | 2018-08-19 | 2 | -12/+28 |
|\ | | | | | ice40: make PLL packing more robust | ||||
| * | ice40: make PLL packing more robust | Sergiusz Bazanski | 2018-08-19 | 2 | -12/+28 |
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* | | Add more missing iCE40 gfx (LP/HX is complete now) | Clifford Wolf | 2018-08-19 | 3 | -4/+47 |
| | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
* | | Add iCE40 gfx for carry chain pips and LUT cascade pips | Clifford Wolf | 2018-08-19 | 1 | -5/+43 |
| | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
* | | Fix iCE40 pip gfx for pips on the top edge of a switchbox | Clifford Wolf | 2018-08-19 | 1 | -5/+5 |
| | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
* | | Add iCE40 gfx for IO span-4 corners | Clifford Wolf | 2018-08-19 | 3 | -3/+36 |
| | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
* | | Add iCE40 gfx for span-4 wires between IO tiles | Clifford Wolf | 2018-08-19 | 5 | -7/+126 |
|/ | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
* | Merge pull request #47 from YosysHQ/settings_propagate | Clifford Wolf | 2018-08-18 | 4 | -16/+5 |
|\ | | | | | Use settings for placer1 and router1 | ||||
| * | Save settings and give nicer names to some | Miodrag Milanovic | 2018-08-10 | 2 | -3/+3 |
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| * | Use settings for placer1 and router1 | Miodrag Milanovic | 2018-08-09 | 2 | -13/+2 |
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* | | Add iCE40 gfx for wires connecting fabric tiles and IO tiles | Clifford Wolf | 2018-08-18 | 4 | -2/+261 |
| | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
* | | Improve iCE40 gfx for IO tiles and RAM tiles | Clifford Wolf | 2018-08-18 | 5 | -23/+243 |
| | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
* | | Add ice40 wire attributes (grid position, segment list) | Clifford Wolf | 2018-08-18 | 3 | -18/+45 |
| | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
* | | Merge branch 'master' of github.com:YosysHQ/nextpnr into archattr | Clifford Wolf | 2018-08-18 | 1 | -4/+6 |
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