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* Add getBelHidden and add some missing "override" statements.Keith Rothman2021-02-111-1/+1
* Add BaseArchRanges for default ArchRanges typesgatecat2021-02-091-16/+1
* Merge pull request #568 from YosysHQ/dave/arch-overridegatecat2021-02-084-184/+117
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| * Use 'T' postfix to disambiguate LHS and RHS of usingD. Shah2021-02-081-21/+21
| * Add archArgs and archArgsToId to Arch APID. Shah2021-02-051-2/+3
| * ice40: Switch to BaseArchD. Shah2021-02-054-182/+114
* | Use RelSlice::ssize instead of cast-to-int throughoutD. Shah2021-02-081-3/+3
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* Mark IdString and IdStringList single argument constructors explicit.Keith Rothman2021-02-043-6/+6
* ice40: Use snake case for arch-specific functionsD. Shah2021-02-037-50/+50
* ice40: Implement IdStringList for all arch object namesD. Shah2021-02-025-57/+88
* refactor: Replace getXName().c_str(ctx) with ctx->nameOfXD. Shah2021-02-022-6/+5
* arch: Add getNameDelimiter API for string listsD. Shah2021-02-021-0/+1
* Run "make clangformat".Keith Rothman2021-02-024-28/+21
* Add pybindings for new APIs.Keith Rothman2021-02-022-0/+14
* Rename Partition -> BelBucket.Keith Rothman2021-02-023-29/+29
* Add Partition APIs to ice40, nexus, gowin archs.Keith Rothman2021-02-023-0/+78
* Initial refactoring of placer API.Keith Rothman2021-02-021-0/+5
* Seperate PipRange types in pybindings_shared.Keith Rothman2021-02-011-0/+4
* cleanup: Spelling fixesD. Shah2021-01-281-1/+1
* cleanup: Remove dead/unused codeD. Shah2021-01-281-32/+0
* Move RelPtr/RelSlice out of arches into commonD. Shah2021-01-271-42/+1
* ice40: Switch from RelPtr to RelSliceD. Shah2021-01-276-149/+137
* ice40: Nicer error for unconstrained SB_GB_IODavid Shah2020-12-271-0/+2
* Use std::string::find(char c) when searching for a single character.Tim Callahan2020-12-161-1/+1
* ice40: Clarify feedback paths in PLL constraints codeDavid Shah2020-12-031-3/+3
* ice40: Derive PLL timing constraintsDavid Shah2020-12-031-31/+138
* RelPtr: remove copy constructor and copy assignmentDavid Shah2020-11-131-0/+3
* ice40/pack/SB_PLL: Force fixed value to 4'b1111 if dynamic delay is usedSylvain Munaut2020-11-101-7/+9
* Remove wire alias APIDavid Shah2020-10-151-9/+0
* CMake: fix Windows-ism in status messagewhitequark2020-08-261-1/+1
* Fix MESSAGE indicating where externally-built .bbas live.William D. Jones2020-08-221-1/+1
* Initial conversion to pybind11Miodrag Milanovic2020-07-231-19/+17
* ice40: If IO is used by SB_GB_IO, can't use it for PLLSylvain Munaut2020-07-091-1/+2
* Fixes for new part typesMiodrag Milanovic2020-07-085-16/+43
* Use proper names in GUIMiodrag Milanovic2020-07-081-12/+12
* Support rest of partsMiodrag Milanovic2020-07-083-13/+58
* Missed adding optionMiodrag Milanovic2020-07-081-0/+2
* Adding LP4K as wellMiodrag Milanovic2020-07-083-3/+16
* Support 4K parts directlyMiodrag Milanovic2020-07-083-5/+33
* Merge pull request #463 from YosysHQ/fix-archcheckDavid Shah2020-07-022-2/+6
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| * ice40: Fix getBelsByTileDavid Shah2020-06-292-2/+6
* | CMake: fix path checks in chipdb build scripts.whitequark2020-07-011-1/+1
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* Make python bindings consistentMiodrag Milanovic2020-06-272-2/+4
* Fix clangformat and execute itMiodrag Milanovic2020-06-271-6/+4
* Update git ignore locationsMiodrag Milanovic2020-06-271-1/+1
* Simplify and improve chipdb embedding/loading.whitequark2020-06-268-152/+62
* CMake: require at least version 3.5 (Ubuntu 16.04).whitequark2020-06-251-1/+1
* CMake: rewrite chipdb handling from ground up.whitequark2020-06-255-127/+145
* ice40: Add fallback behavior for Extra Cell config bits vectorsSylvain Munaut2020-06-021-1/+11
* ice40: Add support for the 2nd bit of SHIFTREG_DIV_MODESylvain Munaut2020-06-021-1/+1
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