aboutsummaryrefslogtreecommitdiffstats
path: root/fpga_interchange/examples/tests/lut_nexus/run.tcl
blob: 4aa56c138d5d3bf86eda8038d884fb004305822b (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
yosys -import

read_verilog $::env(SOURCES)

synth_nexus -noccu2 -nobram -nolutram -nowidelut

# opt_expr -undriven makes sure all nets are driven, if only by the $undef
# net.
opt_expr -undriven
opt_clean

setundef -zero -params

write_json $::env(OUT_JSON)