4 files changed, 91 insertions, 0 deletions
diff --git a/src/vhdl-demo/.gitignore b/src/vhdl-demo/.gitignore
new file mode 100644
index 0000000..796b96d
--- /dev/null
+++ b/src/vhdl-demo/.gitignore
@@ -0,0 +1 @@
+/build
diff --git a/src/vhdl-demo/Makefile b/src/vhdl-demo/Makefile
new file mode 100644
index 0000000..8a68e1f
--- /dev/null
+++ b/src/vhdl-demo/Makefile
@@ -0,0 +1,45 @@
+PREFIX=../..
+BINDIR=${PREFIX}/bin
+
+YOSYS=${BINDIR}/yosys
+NEXTPNR=${BINDIR}/nextpnr-ice40
+ICEPACK=${BINDIR}/icepack
+ICETIME=${BINDIR}/icetime
+FLASH=${BINDIR}/flash
+GHDL=${BINDIR}/ghdl
+
+BUILDDIR  = ./build
+FPGA_TYPE = hx8k
+FPGA_PKG  = ct256
+PCF       = ice40hx8k-evb.pcf
+RMDIR     = rmdir
+
+# Targets
+top: $(BUILDDIR)/top.rpt $(BUILDDIR)/top.bin
+
+flash: $(BUILDDIR)/top.bin
+	${FLASH} $(BUILDDIR)/top.bin
+
+$(BUILDDIR)/%.json: %.vhd
+	@mkdir -p $(@D)
+	${YOSYS} -m ghdl -ql $(subst .json,,$@).log -p 'ghdl $< -e ${<:%.vhd=%}; synth_ice40 -abc9 -device u -top top -json $@'
+
+%.asc: %.json
+	${NEXTPNR} --${FPGA_TYPE} --package ${FPGA_PKG} --json $< --pcf ${PCF} --asc $@
+
+%.bin: %.asc
+	${ICEPACK} $< $@
+
+%.rpt: %.asc
+	${ICETIME} -d $(FPGA_TYPE) -mtr $@ $<
+
+all: top
+
+clean:
+	rm -f $(BUILDDIR)/*.asc $(BUILDDIR)/*.bin $(BUILDDIR)/*.rpt $(BUILDDIR)/*.log $(BUILDDIR)/*.json
+	$(RMDIR) $(BUILDDIR)
+
+# Uncomment this line if you want to keep the intermediate .json and .asc files
+# .PRECIOUS: $(BUILDDIR)/%.json %.asc
+
+.PHONY: all prog clean top
diff --git a/src/vhdl-demo/ice40hx8k-evb.pcf b/src/vhdl-demo/ice40hx8k-evb.pcf
new file mode 100644
index 0000000..43f6208
--- /dev/null
+++ b/src/vhdl-demo/ice40hx8k-evb.pcf
@@ -0,0 +1,5 @@
+set_io CLK100MHZ J3
+set_io btns[0] K11
+set_io btns[1] P13
+set_io leds[0] M12
+set_io leds[1] R16
diff --git a/src/vhdl-demo/top.vhd b/src/vhdl-demo/top.vhd
new file mode 100644
index 0000000..99d0293
--- /dev/null
+++ b/src/vhdl-demo/top.vhd
@@ -0,0 +1,40 @@
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.NUMERIC_STD.ALL;
+
+
+entity top is
+  port (
+    CLK100MHZ: in std_logic;
+
+    -- various stuff defined in the xdc file needs to be defined somewhere
+    leds: out std_logic_vector(1 downto 0);
+    btns: in std_logic_vector(1 downto 0)
+
+  );
+end top;
+
+
+architecture rtl of top is
+  signal led: std_logic;
+begin
+  resetLogic: process (CLK100MHZ)
+    variable i: unsigned(31 downto 0) := to_unsigned(0, 32);
+  begin
+    if rising_edge(CLK100MHZ) then
+      if i >= to_unsigned(100000000, 32) then
+	led <= not led;	
+	i := to_unsigned(0,32);
+      else
+        i := i + 1;
+      end if;
+    end if;
+  end process;
+
+  leds(0) <= led;
+  leds(1) <= not led;
+end rtl;
+
+
+  
+