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| author | Clifford Wolf <clifford@clifford.at> | 2016-09-18 00:50:02 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2016-09-18 00:50:02 +0200 |
| commit | 0ead5a9e44fecf0712658efd168ebd7868039867 (patch) | |
| tree | 9a3e6d03943a0f2b152dc3378d916add1bd5658a | |
| parent | 7bc88e81010d5e641a55da9fb99724a90a2a4efa (diff) | |
| parent | d8ad889594cb5746d3d0b1f7590eeaf63d13c64a (diff) | |
| download | yosys-0ead5a9e44fecf0712658efd168ebd7868039867.tar.gz yosys-0ead5a9e44fecf0712658efd168ebd7868039867.tar.bz2 yosys-0ead5a9e44fecf0712658efd168ebd7868039867.zip | |
Merge branch 'master' of github.com:cliffordwolf/yosys
| -rw-r--r-- | passes/techmap/techmap.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/passes/techmap/techmap.cc b/passes/techmap/techmap.cc index 1ab6df1dc..b2cc492b2 100644 --- a/passes/techmap/techmap.cc +++ b/passes/techmap/techmap.cc @@ -639,7 +639,7 @@ struct TechmapWorker if (techmap_cache.count(key) > 0) { tpl = techmap_cache[key]; } else { - if (cell->parameters.size() != 0) { + if (parameters.size() != 0) { derived_name = tpl->derive(map, dict<RTLIL::IdString, RTLIL::Const>(parameters.begin(), parameters.end())); tpl = map->module(derived_name); log_continue = true; |