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| author | Andrew Zonenberg <azonenberg@drawersteak.com> | 2016-03-26 23:29:02 -0700 |
|---|---|---|
| committer | Andrew Zonenberg <azonenberg@drawersteak.com> | 2016-03-26 23:29:02 -0700 |
| commit | 3197b6c3721b4985b5a5e4223ce7092e27f750c7 (patch) | |
| tree | ca4ca8c659dcc0117352d282f584bd6909c06acf | |
| parent | 31a7567affb7425af1aa27d6dcda4666859ce62f (diff) | |
| download | yosys-3197b6c3721b4985b5a5e4223ce7092e27f750c7.tar.gz yosys-3197b6c3721b4985b5a5e4223ce7092e27f750c7.tar.bz2 yosys-3197b6c3721b4985b5a5e4223ce7092e27f750c7.zip | |
Added GP_COUNT8/GP_COUNT14 cells
| -rw-r--r-- | techlibs/greenpak4/cells_sim.v | 22 |
1 files changed, 22 insertions, 0 deletions
diff --git a/techlibs/greenpak4/cells_sim.v b/techlibs/greenpak4/cells_sim.v index a4094f06d..6b5100f75 100644 --- a/techlibs/greenpak4/cells_sim.v +++ b/techlibs/greenpak4/cells_sim.v @@ -82,3 +82,25 @@ module GP_LFOSC(input PWRDN, output reg CLKOUT); end endmodule + +module GP_COUNT8(input CLK, input wire RST, output reg OUT); + + parameter RESET_MODE = "RISING"; + + parameter COUNT_TO = 8'h1; + parameter CLKIN_DIVIDE = 1; + + //more complex hard IP blocks are not supported for simulation yet + +endmodule + +module GP_COUNT14(input CLK, input wire RST, output reg OUT); + + parameter RESET_MODE = "RISING"; + + parameter COUNT_TO = 14'h1; + parameter CLKIN_DIVIDE = 1; + + //more complex hard IP blocks are not supported for simulation yet + +endmodule |