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| author | Eddie Hung <eddie@fpgeh.com> | 2019-10-05 09:27:12 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-10-05 09:27:12 -0700 |
| commit | 5c68da4150f8e5367138f2c7187f707b20cc19db (patch) | |
| tree | 5ffecc91ae6827340b3261d91e077215eb9c4157 | |
| parent | b47bb5c8100bf24c7075dc322f201779eda280b7 (diff) | |
| download | yosys-5c68da4150f8e5367138f2c7187f707b20cc19db.tar.gz yosys-5c68da4150f8e5367138f2c7187f707b20cc19db.tar.bz2 yosys-5c68da4150f8e5367138f2c7187f707b20cc19db.zip | |
Missing 'accept' at end of ice40_wrapcarry, spotted by @cliffordwolf
| -rw-r--r-- | passes/pmgen/ice40_wrapcarry.pmg | 4 | ||||
| -rw-r--r-- | tests/ice40/wrapcarry.ys | 22 |
2 files changed, 26 insertions, 0 deletions
diff --git a/passes/pmgen/ice40_wrapcarry.pmg b/passes/pmgen/ice40_wrapcarry.pmg index 9e64c7467..bb59edb0c 100644 --- a/passes/pmgen/ice40_wrapcarry.pmg +++ b/passes/pmgen/ice40_wrapcarry.pmg @@ -9,3 +9,7 @@ match lut index <SigSpec> port(lut, \I1) === port(carry, \I0) index <SigSpec> port(lut, \I2) === port(carry, \I1) endmatch + +code + accept; +endcode diff --git a/tests/ice40/wrapcarry.ys b/tests/ice40/wrapcarry.ys new file mode 100644 index 000000000..10c029e68 --- /dev/null +++ b/tests/ice40/wrapcarry.ys @@ -0,0 +1,22 @@ +read_verilog <<EOT +module top(input A, B, CI, output O, CO); + SB_CARRY carry ( + .I0(A), + .I1(B), + .CI(CI), + .CO(CO) + ); + SB_LUT4 #( + .LUT_INIT(16'b 0110_1001_1001_0110) + ) adder ( + .I0(1'b0), + .I1(A), + .I2(B), + .I3(1'b0), + .O(O) + ); +endmodule +EOT + +ice40_wrapcarry +select -assert-count 1 t:$__ICE40_CARRY_WRAPPER |