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| author | Clifford Wolf <clifford@clifford.at> | 2019-05-03 15:29:44 +0200 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2019-05-03 15:29:44 +0200 |
| commit | 71ede7cb05ae35c90eccb80ffc413b4559ba7e60 (patch) | |
| tree | 73229c3e02655a9fd3c9f2bb987f44b226d65fc7 | |
| parent | 97423caddaafa0fbaca6f541a9c3e17f036b198b (diff) | |
| parent | 6bbe2fdbf32e6335cdbecc21547e54992c3a606d (diff) | |
| download | yosys-71ede7cb05ae35c90eccb80ffc413b4559ba7e60.tar.gz yosys-71ede7cb05ae35c90eccb80ffc413b4559ba7e60.tar.bz2 yosys-71ede7cb05ae35c90eccb80ffc413b4559ba7e60.zip | |
Merge pull request #976 from YosysHQ/clifford/fix974
Fix width detection of memory access with bit slice
| -rw-r--r-- | frontends/ast/genrtlil.cc | 2 | ||||
| -rw-r--r-- | frontends/ast/simplify.cc | 1 | ||||
| -rw-r--r-- | tests/simple/mem2reg.v | 22 |
3 files changed, 25 insertions, 0 deletions
diff --git a/frontends/ast/genrtlil.cc b/frontends/ast/genrtlil.cc index b3a2a84be..d4515babf 100644 --- a/frontends/ast/genrtlil.cc +++ b/frontends/ast/genrtlil.cc @@ -645,6 +645,8 @@ void AstNode::detectSignWidthWorker(int &width_hint, bool &sign_hint, bool *foun if (!id_ast->children[0]->range_valid) log_file_error(filename, linenum, "Failed to detect width of memory access `%s'!\n", str.c_str()); this_width = id_ast->children[0]->range_left - id_ast->children[0]->range_right + 1; + if (children.size() > 1) + range = children[1]; } else log_file_error(filename, linenum, "Failed to detect width for identifier %s!\n", str.c_str()); if (range) { diff --git a/frontends/ast/simplify.cc b/frontends/ast/simplify.cc index 4d4b9dfe1..d6561682a 100644 --- a/frontends/ast/simplify.cc +++ b/frontends/ast/simplify.cc @@ -1607,6 +1607,7 @@ skip_dynamic_range_lvalue_expansion:; current_scope[wire_tmp->str] = wire_tmp; wire_tmp->attributes["\\nosync"] = AstNode::mkconst_int(1, false); while (wire_tmp->simplify(true, false, false, 1, -1, false, false)) { } + wire_tmp->is_logic = true; AstNode *wire_tmp_id = new AstNode(AST_IDENTIFIER); wire_tmp_id->str = wire_tmp->str; diff --git a/tests/simple/mem2reg.v b/tests/simple/mem2reg.v index 9839fd4a8..100426785 100644 --- a/tests/simple/mem2reg.v +++ b/tests/simple/mem2reg.v @@ -92,3 +92,25 @@ module mem2reg_test5(input ctrl, output out); assign out = bar[foo[0]]; endmodule +// ------------------------------------------------------ + +module mem2reg_test6 (din, dout); + input wire [3:0] din; + output reg [3:0] dout; + + reg [1:0] din_array [1:0]; + reg [1:0] dout_array [1:0]; + + always @* begin + din_array[0] = din[0 +: 2]; + din_array[1] = din[2 +: 2]; + + dout_array[0] = din_array[0]; + dout_array[1] = din_array[1]; + + {dout_array[0][1], dout_array[0][0]} = dout_array[0][0] + dout_array[1][0]; + + dout[0 +: 2] = dout_array[0]; + dout[2 +: 2] = dout_array[1]; + end +endmodule |