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| author | Eddie Hung <eddie@fpgeh.com> | 2019-04-16 13:16:20 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-04-16 13:16:20 -0700 |
| commit | aece97024de574fd765e18e31f685e9ffb0a13c6 (patch) | |
| tree | 88776f676c01d05cb2b15c3d04c6d3b60ad4f230 | |
| parent | fc5fda595d2695d1f29f68f0527052e99c301db8 (diff) | |
| download | yosys-aece97024de574fd765e18e31f685e9ffb0a13c6.tar.gz yosys-aece97024de574fd765e18e31f685e9ffb0a13c6.tar.bz2 yosys-aece97024de574fd765e18e31f685e9ffb0a13c6.zip | |
Fix spacing
| -rw-r--r-- | backends/aiger/xaiger.cc | 2 | ||||
| -rw-r--r-- | techlibs/xilinx/cells.lut | 2 |
2 files changed, 2 insertions, 2 deletions
diff --git a/backends/aiger/xaiger.cc b/backends/aiger/xaiger.cc index 875a2ec03..bd7347a19 100644 --- a/backends/aiger/xaiger.cc +++ b/backends/aiger/xaiger.cc @@ -576,7 +576,7 @@ struct XAigerWriter RTLIL::Module *holes_module = nullptr; holes_module = module->design->addModule("\\__holes__"); - + for (auto cell : box_list) { int box_inputs = 0, box_outputs = 0; int box_id = module->design->module(cell->type)->attributes.at("\\abc_box_id").as_int(); diff --git a/techlibs/xilinx/cells.lut b/techlibs/xilinx/cells.lut index a1d9b9c42..c6bc7b1f7 100644 --- a/techlibs/xilinx/cells.lut +++ b/techlibs/xilinx/cells.lut @@ -1,4 +1,4 @@ -# Max delays from https://pastebin.com/v2hrcksd +# Max delays from https://pastebin.com/v2hrcksd # from https://github.com/SymbiFlow/prjxray/pull/706#issuecomment-479380321 # K area delay |