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| author | Clifford Wolf <clifford@clifford.at> | 2019-05-03 20:34:32 +0200 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2019-05-03 20:34:32 +0200 |
| commit | f170fb6383477af453ca90ce4f67102e98b03f6e (patch) | |
| tree | 40ab4b7a7d67c8644a12ce1ac28dabf40536cb62 | |
| parent | 71ede7cb05ae35c90eccb80ffc413b4559ba7e60 (diff) | |
| parent | 1d43a25f08920643f413cf74b18adfb32815fcd8 (diff) | |
| download | yosys-f170fb6383477af453ca90ce4f67102e98b03f6e.tar.gz yosys-f170fb6383477af453ca90ce4f67102e98b03f6e.tar.bz2 yosys-f170fb6383477af453ca90ce4f67102e98b03f6e.zip | |
Merge pull request #984 from YosysHQ/eddie/fix_982
dffinit to do nothing when (* init *) value is 1'bx
| -rw-r--r-- | passes/techmap/dffinit.cc | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/passes/techmap/dffinit.cc b/passes/techmap/dffinit.cc index 48390488e..0ad33dc0e 100644 --- a/passes/techmap/dffinit.cc +++ b/passes/techmap/dffinit.cc @@ -102,7 +102,8 @@ struct DffinitPass : public Pass { if (wire->attributes.count("\\init")) { Const value = wire->attributes.at("\\init"); for (int i = 0; i < min(GetSize(value), GetSize(wire)); i++) - init_bits[sigmap(SigBit(wire, i))] = value[i]; + if (value[i] != State::Sx) + init_bits[sigmap(SigBit(wire, i))] = value[i]; } if (wire->port_output) for (auto bit : sigmap(wire)) |