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| author | whitequark <whitequark@whitequark.org> | 2020-06-09 06:26:02 +0000 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2020-06-09 06:26:02 +0000 |
| commit | 4351194e8ce94e7078b67a20e5fc92777d6cb3e6 (patch) | |
| tree | 7d2027cda96eeb6c16506ca8b1c9df2fe475efa7 /README.md | |
| parent | 83f84afc0b617fe78fb7cfa31fb9d1cd202e22f2 (diff) | |
| parent | 53688a24b531adcc99c091f728e9657d16010467 (diff) | |
| download | yosys-4351194e8ce94e7078b67a20e5fc92777d6cb3e6.tar.gz yosys-4351194e8ce94e7078b67a20e5fc92777d6cb3e6.tar.bz2 yosys-4351194e8ce94e7078b67a20e5fc92777d6cb3e6.zip | |
Merge pull request #2107 from whitequark/flatten-hdlname
flatten: preserve original object names
Diffstat (limited to 'README.md')
| -rw-r--r-- | README.md | 4 |
1 files changed, 3 insertions, 1 deletions
@@ -309,7 +309,9 @@ Verilog Attributes and non-standard features that have ports with a width that depends on a parameter. - The ``hdlname`` attribute is used by some passes to document the original - (HDL) name of a module when renaming a module. + (HDL) name of a module when renaming a module. It should contain a single + name, or, when describing a hierarchical name in a flattened design, multiple + names separated by a single space character. - The ``keep`` attribute on cells and wires is used to mark objects that should never be removed by the optimizer. This is used for example for cells that |