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| author | Marcelina Kościelnicka <mwk@0x04.net> | 2020-12-17 00:24:48 +0100 |
|---|---|---|
| committer | Marcelina Kościelnicka <mwk@0x04.net> | 2020-12-17 03:25:07 +0100 |
| commit | 871fc34ad43dac0ff924b8f72a0524d937040190 (patch) | |
| tree | cc1837956ea7816b5990ec2bfbb2c3290ff49dba /backends/cxxrtl | |
| parent | 40e35993af6ecb6207f15cc176455ff8d66bcc69 (diff) | |
| download | yosys-871fc34ad43dac0ff924b8f72a0524d937040190.tar.gz yosys-871fc34ad43dac0ff924b8f72a0524d937040190.tar.bz2 yosys-871fc34ad43dac0ff924b8f72a0524d937040190.zip | |
xilinx: Add FDDRCPE and FDDRRSE blackbox cells.
These are necessary primitives for proper DDR support on Virtex 2 and
Spartan 3.
Diffstat (limited to 'backends/cxxrtl')
0 files changed, 0 insertions, 0 deletions