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| author | georgerennie <georgerennie@gmail.com> | 2020-12-01 01:37:19 +0000 |
|---|---|---|
| committer | georgerennie <georgerennie@gmail.com> | 2020-12-01 01:37:19 +0000 |
| commit | c1f6ce8b33b1c06a4e38b621e27876d5715eb26d (patch) | |
| tree | ef64f8bd35b8ed518ba347b91ef41494e4d15527 /backends/cxxrtl | |
| parent | 2116c585810cddb73777b46ea9aad0d6d511d82b (diff) | |
| download | yosys-c1f6ce8b33b1c06a4e38b621e27876d5715eb26d.tar.gz yosys-c1f6ce8b33b1c06a4e38b621e27876d5715eb26d.tar.bz2 yosys-c1f6ce8b33b1c06a4e38b621e27876d5715eb26d.zip | |
Fix SYNTHESIS always being defined in Verilog frontend
Diffstat (limited to 'backends/cxxrtl')
0 files changed, 0 insertions, 0 deletions