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| author | whitequark <whitequark@whitequark.org> | 2020-12-19 04:14:31 +0000 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2020-12-19 04:14:31 +0000 |
| commit | ab9e2f4fda1da455643579537d0ae6ffc6d46aab (patch) | |
| tree | e292e0193ad5f61409c9f2581d62a036653dc93d /backends/verilog | |
| parent | eaf6b551b68f44bc31c2d4274c91944451b01649 (diff) | |
| parent | d889a3df35e539b6dcfbee9c6a98461eca1a0b0e (diff) | |
| download | yosys-ab9e2f4fda1da455643579537d0ae6ffc6d46aab.tar.gz yosys-ab9e2f4fda1da455643579537d0ae6ffc6d46aab.tar.bz2 yosys-ab9e2f4fda1da455643579537d0ae6ffc6d46aab.zip | |
Merge pull request #2487 from whitequark/cxxrtl-outlining
CXXRTL: implement zero-cost full coverage debug information through the magic✨ of outlining🪄🎀🧹
Diffstat (limited to 'backends/verilog')
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