Merge branch 'master' of github.com:YosysHQ/yosys

1 files changed, 5 insertions, 5 deletions

diff --git a/examples/anlogic/demo.v b/examples/anlogic/demo.v
index a7edf4e37..e17db771e 100644
--- a/examples/anlogic/demo.v
+++ b/examples/anlogic/demo.v
@@ -1,18 +1,18 @@
 module demo (
-    input wire CLK_IN,  
-    output wire R_LED 
+    input wire CLK_IN,
+    output wire R_LED
 );
     parameter time1 = 30'd12_000_000;
     reg led_state;
     reg [29:0] count;
-    
+
     always @(posedge CLK_IN)begin
         if(count == time1)begin
-            count<= 30'd0; 	
+            count<= 30'd0;
             led_state <= ~led_state;
         end
         else
             count <= count + 1'b1;
     end
     assign R_LED = led_state;
-endmodule
\ No newline at end of file
+endmodule