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| author | Eddie Hung <eddie@fpgeh.com> | 2019-05-27 12:16:10 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-05-27 12:16:10 -0700 |
| commit | 234156c01a4086a69ff9ac9f6ae668d64734d525 (patch) | |
| tree | 15674d1e6679a4c45fd28e8275c47f7d0cfdf2b2 /frontends/aiger/aigerparse.cc | |
| parent | 03b289a851c62eb2a7e3592432876bfa8a56770b (diff) | |
| download | yosys-234156c01a4086a69ff9ac9f6ae668d64734d525.tar.gz yosys-234156c01a4086a69ff9ac9f6ae668d64734d525.tar.bz2 yosys-234156c01a4086a69ff9ac9f6ae668d64734d525.zip | |
Instantiate cell type (from sym file) otherwise 'clean' warnings
Diffstat (limited to 'frontends/aiger/aigerparse.cc')
| -rw-r--r-- | frontends/aiger/aigerparse.cc | 9 |
1 files changed, 6 insertions, 3 deletions
diff --git a/frontends/aiger/aigerparse.cc b/frontends/aiger/aigerparse.cc index 2441ee937..6c174871b 100644 --- a/frontends/aiger/aigerparse.cc +++ b/frontends/aiger/aigerparse.cc @@ -720,14 +720,17 @@ void AigerReader::post_process() } else log_abort(); - std::string port; - mf >> port; + std::string port, type; + mf >> port >> type; RTLIL::IdString cell_name = RTLIL::escape_id(symbol); RTLIL::IdString cell_port = RTLIL::escape_id(port); + RTLIL::IdString cell_type = RTLIL::escape_id(type); RTLIL::Cell* cell = module->cell(cell_name); if (!cell) - cell = module->addCell(cell_name, "$__blackbox__"); + cell = module->addCell(cell_name, cell_type); + else + log_assert(cell->type == cell_type); wire->port_input = false; wire->port_output = false; if (cell->hasPort(cell_port)) { |