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| author | Miodrag Milanovic <mmicko@gmail.com> | 2019-08-18 11:47:46 +0200 |
|---|---|---|
| committer | Miodrag Milanovic <mmicko@gmail.com> | 2019-08-18 11:47:46 +0200 |
| commit | 4a32e29445f65edd1726808a7353a9d0e2560c00 (patch) | |
| tree | 179544dd193fe72b3658269cb22a6eae66bee8a1 /frontends/ast/ast.cc | |
| parent | 5f561bdcb1d562d6f975b4a27beca1b8b7af908f (diff) | |
| parent | 98a54353b7d893752d856b3726853d4921c6aa1f (diff) | |
| download | yosys-4a32e29445f65edd1726808a7353a9d0e2560c00.tar.gz yosys-4a32e29445f65edd1726808a7353a9d0e2560c00.tar.bz2 yosys-4a32e29445f65edd1726808a7353a9d0e2560c00.zip | |
Merge remote-tracking branch 'upstream/master' into anlogic_fixes
Diffstat (limited to 'frontends/ast/ast.cc')
| -rw-r--r-- | frontends/ast/ast.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/frontends/ast/ast.cc b/frontends/ast/ast.cc index 07ef0a86e..0d6626b19 100644 --- a/frontends/ast/ast.cc +++ b/frontends/ast/ast.cc @@ -1172,7 +1172,7 @@ void AST::process(RTLIL::Design *design, AstNode *ast, bool dump_ast1, bool dump if (design->has((*it)->str)) { RTLIL::Module *existing_mod = design->module((*it)->str); - if (!nooverwrite && !overwrite && !existing_mod->get_bool_attribute("\\blackbox")) { + if (!nooverwrite && !overwrite && !existing_mod->get_blackbox_attribute()) { log_file_error((*it)->filename, (*it)->linenum, "Re-definition of module `%s'!\n", (*it)->str.c_str()); } else if (nooverwrite) { log("Ignoring re-definition of module `%s' at %s:%d.\n", |