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author | Eddie Hung <eddie@fpgeh.com> | 2019-08-18 21:29:15 -0700 |
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committer | Eddie Hung <eddie@fpgeh.com> | 2019-08-18 21:29:15 -0700 |
commit | e34f2de55d9d1ec8cbdd9c1f3e27af678f0fc2df (patch) | |
tree | 74c0b3ba63fdd678fcfc839dd6d0d39d43cef365 /frontends/ast/ast.cc | |
parent | f5170a7eda6fddaf482896a2ad67da4bb3131d7b (diff) | |
parent | 98a54353b7d893752d856b3726853d4921c6aa1f (diff) | |
download | yosys-e34f2de55d9d1ec8cbdd9c1f3e27af678f0fc2df.tar.gz yosys-e34f2de55d9d1ec8cbdd9c1f3e27af678f0fc2df.tar.bz2 yosys-e34f2de55d9d1ec8cbdd9c1f3e27af678f0fc2df.zip |
Merge remote-tracking branch 'origin/master' into clifford/testfast
Diffstat (limited to 'frontends/ast/ast.cc')
-rw-r--r-- | frontends/ast/ast.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/frontends/ast/ast.cc b/frontends/ast/ast.cc index 07ef0a86e..0d6626b19 100644 --- a/frontends/ast/ast.cc +++ b/frontends/ast/ast.cc @@ -1172,7 +1172,7 @@ void AST::process(RTLIL::Design *design, AstNode *ast, bool dump_ast1, bool dump if (design->has((*it)->str)) { RTLIL::Module *existing_mod = design->module((*it)->str); - if (!nooverwrite && !overwrite && !existing_mod->get_bool_attribute("\\blackbox")) { + if (!nooverwrite && !overwrite && !existing_mod->get_blackbox_attribute()) { log_file_error((*it)->filename, (*it)->linenum, "Re-definition of module `%s'!\n", (*it)->str.c_str()); } else if (nooverwrite) { log("Ignoring re-definition of module `%s' at %s:%d.\n", |