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| author | Clifford Wolf <clifford@clifford.at> | 2019-09-20 13:30:28 +0200 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2019-09-20 13:30:28 +0200 |
| commit | f3781f98db227f160e08b2fc7cf8c61f663a56c9 (patch) | |
| tree | 7d16d0a2c04b9aead04e7f46253e2b35a4e4b309 /frontends/ast/ast.h | |
| parent | c072e00a393319f3ff338291798f52038eda11fe (diff) | |
| parent | 8da0888bf6ae4c975c6d3b0c9a656bc10e1283e4 (diff) | |
| download | yosys-f3781f98db227f160e08b2fc7cf8c61f663a56c9.tar.gz yosys-f3781f98db227f160e08b2fc7cf8c61f663a56c9.tar.bz2 yosys-f3781f98db227f160e08b2fc7cf8c61f663a56c9.zip | |
Merge pull request #1386 from YosysHQ/clifford/fix1360
Fix handling of read_verilog config in AstModule::reprocess_module()
Diffstat (limited to 'frontends/ast/ast.h')
| -rw-r--r-- | frontends/ast/ast.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/frontends/ast/ast.h b/frontends/ast/ast.h index 54b2fb319..93fee913e 100644 --- a/frontends/ast/ast.h +++ b/frontends/ast/ast.h @@ -299,6 +299,7 @@ namespace AST std::string derive_common(RTLIL::Design *design, dict<RTLIL::IdString, RTLIL::Const> parameters, AstNode **new_ast_out, bool mayfail); void reprocess_module(RTLIL::Design *design, dict<RTLIL::IdString, RTLIL::Module *> local_interfaces) YS_OVERRIDE; RTLIL::Module *clone() const YS_OVERRIDE; + void loadconfig() const; }; // this must be set by the language frontend before parsing the sources |