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| author | Clifford Wolf <clifford@clifford.at> | 2013-12-27 14:20:15 +0100 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2013-12-27 14:20:15 +0100 |
| commit | 369bf81a7049c96f62af084bb5007fbf45e36ab4 (patch) | |
| tree | 92071580c9bd60888ee5861d59457947a8adfde7 /frontends/ast/genrtlil.cc | |
| parent | ecc30255ba70910777a4586f5bd6abc818073293 (diff) | |
| download | yosys-369bf81a7049c96f62af084bb5007fbf45e36ab4.tar.gz yosys-369bf81a7049c96f62af084bb5007fbf45e36ab4.tar.bz2 yosys-369bf81a7049c96f62af084bb5007fbf45e36ab4.zip | |
Added support for non-const === and !== (for miter circuits)
Diffstat (limited to 'frontends/ast/genrtlil.cc')
| -rw-r--r-- | frontends/ast/genrtlil.cc | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/frontends/ast/genrtlil.cc b/frontends/ast/genrtlil.cc index 36ca1432b..1b6fc1d8b 100644 --- a/frontends/ast/genrtlil.cc +++ b/frontends/ast/genrtlil.cc @@ -1119,8 +1119,8 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint) if (0) { case AST_LE: type_name = "$le"; } if (0) { case AST_EQ: type_name = "$eq"; } if (0) { case AST_NE: type_name = "$ne"; } - if (0) { case AST_EQX: type_name = "$eq"; } - if (0) { case AST_NEX: type_name = "$ne"; } + if (0) { case AST_EQX: type_name = "$eqx"; } + if (0) { case AST_NEX: type_name = "$nex"; } if (0) { case AST_GE: type_name = "$ge"; } if (0) { case AST_GT: type_name = "$gt"; } { |