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| author | Clifford Wolf <clifford@clifford.at> | 2013-12-04 21:06:54 +0100 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2013-12-04 21:06:54 +0100 |
| commit | 4a4a3fc3377243d85100b829a0f6b785376cce9f (patch) | |
| tree | 689dda333df9ac7012ce460e8f7e801b631c0882 /frontends/ast/genrtlil.cc | |
| parent | f4b46ed31e5f5c41bbd4ee1fdf996ecdc2010174 (diff) | |
| download | yosys-4a4a3fc3377243d85100b829a0f6b785376cce9f.tar.gz yosys-4a4a3fc3377243d85100b829a0f6b785376cce9f.tar.bz2 yosys-4a4a3fc3377243d85100b829a0f6b785376cce9f.zip | |
Various improvements in support for generate statements
Diffstat (limited to 'frontends/ast/genrtlil.cc')
| -rw-r--r-- | frontends/ast/genrtlil.cc | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/frontends/ast/genrtlil.cc b/frontends/ast/genrtlil.cc index 7ebc4b719..269752df5 100644 --- a/frontends/ast/genrtlil.cc +++ b/frontends/ast/genrtlil.cc @@ -812,6 +812,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint) case AST_GENFOR: case AST_GENBLOCK: case AST_GENIF: + case AST_GENCASE: break; // remember the parameter, needed for example in techmap |