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| author | Clifford Wolf <clifford@clifford.at> | 2013-11-24 17:29:11 +0100 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2013-11-24 17:29:11 +0100 |
| commit | f71e27dbf15d063ca45378ff2eb2d8102220f199 (patch) | |
| tree | 67137e2ddf4dcf588fa4397d15d3e7648805a896 /frontends/ast/genrtlil.cc | |
| parent | 609caa23b5e12547c043dc4a1827d1a531af1992 (diff) | |
| download | yosys-f71e27dbf15d063ca45378ff2eb2d8102220f199.tar.gz yosys-f71e27dbf15d063ca45378ff2eb2d8102220f199.tar.bz2 yosys-f71e27dbf15d063ca45378ff2eb2d8102220f199.zip | |
Remove auto_wire framework (smarter than the verilog standard)
Diffstat (limited to 'frontends/ast/genrtlil.cc')
| -rw-r--r-- | frontends/ast/genrtlil.cc | 10 |
1 files changed, 1 insertions, 9 deletions
diff --git a/frontends/ast/genrtlil.cc b/frontends/ast/genrtlil.cc index 177c1ec59..66b670c7a 100644 --- a/frontends/ast/genrtlil.cc +++ b/frontends/ast/genrtlil.cc @@ -917,15 +917,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint) RTLIL::Wire *wire = new RTLIL::Wire; wire->attributes["\\src"] = stringf("%s:%d", filename.c_str(), linenum); wire->name = str; - if (width_hint >= 0) { - wire->width = width_hint; - log("Warning: Identifier `%s' is implicitly declared with width %d at %s:%d.\n", - str.c_str(), width_hint, filename.c_str(), linenum); - } else { - log("Warning: Identifier `%s' is implicitly declared at %s:%d.\n", - str.c_str(), filename.c_str(), linenum); - } - wire->auto_width = true; + log("Warning: Identifier `%s' is implicitly declared at %s:%d.\n", str.c_str(), filename.c_str(), linenum); current_module->wires[str] = wire; } else if (id2ast->type == AST_PARAMETER || id2ast->type == AST_LOCALPARAM) { |