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| author | Alberto Gonzalez <boqwxp@airmail.cc> | 2020-04-17 06:16:59 +0000 |
|---|---|---|
| committer | Alberto Gonzalez <boqwxp@airmail.cc> | 2020-04-17 06:16:59 +0000 |
| commit | 10a814f97808de8cce7e50a03f01832db66c263e (patch) | |
| tree | 44afa7d32f1137ebfe1a2f7048fdc4c28579ba8f /frontends/verilog/const2ast.cc | |
| parent | c69db910acef73bbd5a1bfb015231fce5419e0af (diff) | |
| download | yosys-10a814f97808de8cce7e50a03f01832db66c263e.tar.gz yosys-10a814f97808de8cce7e50a03f01832db66c263e.tar.bz2 yosys-10a814f97808de8cce7e50a03f01832db66c263e.zip | |
Add Verilog source location information to `AST_POSEDGE` and `AST_NEGEDGE` nodes.
Diffstat (limited to 'frontends/verilog/const2ast.cc')
0 files changed, 0 insertions, 0 deletions