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| author | Eddie Hung <eddie@fpgeh.com> | 2020-01-28 17:41:57 -0800 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2020-01-28 17:41:57 -0800 |
| commit | 0fd64aab25787e2591080cf71192ee16fcf2ae9f (patch) | |
| tree | 74a9b1eb3a584fbdd5221800028180b096b82caf /frontends/verilog/preproc.cc | |
| parent | 7e0e42f907260e76e3c7cb01c907a0cf61a6e326 (diff) | |
| download | yosys-0fd64aab25787e2591080cf71192ee16fcf2ae9f.tar.gz yosys-0fd64aab25787e2591080cf71192ee16fcf2ae9f.tar.bz2 yosys-0fd64aab25787e2591080cf71192ee16fcf2ae9f.zip | |
synth_xilinx: fix help when no active_design; fixes #1664
Diffstat (limited to 'frontends/verilog/preproc.cc')
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