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| author | Miodrag Milanović <mmicko@gmail.com> | 2020-06-18 12:44:21 +0200 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2020-06-18 12:44:21 +0200 |
| commit | 2123019ac6da12fa116955ee397183363a6e5eaf (patch) | |
| tree | e523c5428ab51e9dc2b8f54f2fe5587670c28968 /frontends/verilog/preproc.cc | |
| parent | c4f20f744be57d4628400368d5fce040a9dbf269 (diff) | |
| parent | 60fb9cabcfad985a4f35acaa74fd6e63b45081bc (diff) | |
| download | yosys-2123019ac6da12fa116955ee397183363a6e5eaf.tar.gz yosys-2123019ac6da12fa116955ee397183363a6e5eaf.tar.bz2 yosys-2123019ac6da12fa116955ee397183363a6e5eaf.zip | |
Merge pull request #2164 from madebr/msvc
Get yosys building on Visual Studio
Diffstat (limited to 'frontends/verilog/preproc.cc')
| -rw-r--r-- | frontends/verilog/preproc.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/frontends/verilog/preproc.cc b/frontends/verilog/preproc.cc index 7905ea598..ea23139e2 100644 --- a/frontends/verilog/preproc.cc +++ b/frontends/verilog/preproc.cc @@ -591,7 +591,7 @@ read_define_args() default: // The only FSM states are 0-2 and we dealt with 2 at the start of the loop. - __builtin_unreachable(); + log_assert(false); } } |