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| author | Andrew Zonenberg <azonenberg@drawersteak.com> | 2016-04-22 19:07:55 -0700 |
|---|---|---|
| committer | Andrew Zonenberg <azonenberg@drawersteak.com> | 2016-04-22 19:07:55 -0700 |
| commit | ab11f2aa701f4ff7a8df98d2a4158ea1f661a205 (patch) | |
| tree | d2c8e2b82b7cca57127bd9dd54d3eb40386a88f7 /frontends/verilog/verilog_frontend.cc | |
| parent | d90c1e952256dc00d070863835e061d73e4bc6b3 (diff) | |
| parent | 7311be4028a9caad5a0fac1a3433220b4233ef84 (diff) | |
| download | yosys-ab11f2aa701f4ff7a8df98d2a4158ea1f661a205.tar.gz yosys-ab11f2aa701f4ff7a8df98d2a4158ea1f661a205.tar.bz2 yosys-ab11f2aa701f4ff7a8df98d2a4158ea1f661a205.zip | |
Merge https://github.com/cliffordwolf/yosys
Diffstat (limited to 'frontends/verilog/verilog_frontend.cc')
| -rw-r--r-- | frontends/verilog/verilog_frontend.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/frontends/verilog/verilog_frontend.cc b/frontends/verilog/verilog_frontend.cc index 11c2824c3..f8ccda181 100644 --- a/frontends/verilog/verilog_frontend.cc +++ b/frontends/verilog/verilog_frontend.cc @@ -186,7 +186,7 @@ struct VerilogFrontend : public Frontend { formal_mode = false; default_nettype_wire = true; - log_header("Executing Verilog-2005 frontend.\n"); + log_header(design, "Executing Verilog-2005 frontend.\n"); args.insert(args.begin()+1, verilog_defaults.begin(), verilog_defaults.end()); |