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| author | whitequark <whitequark@whitequark.org> | 2020-06-26 07:30:27 +0000 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2020-06-26 07:30:27 +0000 |
| commit | 12c016ebdc61d3eba681579e7b0b4d81672e498f (patch) | |
| tree | a4b2953cb6ea25865915721b71d2f22a1e06f725 /frontends/verilog/verilog_lexer.l | |
| parent | d6bdc09422e89c30207810cf00021b9ea37991e7 (diff) | |
| parent | 39c39848a21dc4f4a2c3b17842d854047ba6c16f (diff) | |
| download | yosys-12c016ebdc61d3eba681579e7b0b4d81672e498f.tar.gz yosys-12c016ebdc61d3eba681579e7b0b4d81672e498f.tar.bz2 yosys-12c016ebdc61d3eba681579e7b0b4d81672e498f.zip | |
Merge pull request #2188 from antmicro/missing-operators
Add logic-assignments operators
Diffstat (limited to 'frontends/verilog/verilog_lexer.l')
| -rw-r--r-- | frontends/verilog/verilog_lexer.l | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/frontends/verilog/verilog_lexer.l b/frontends/verilog/verilog_lexer.l index e6fa6361e..028106381 100644 --- a/frontends/verilog/verilog_lexer.l +++ b/frontends/verilog/verilog_lexer.l @@ -526,6 +526,12 @@ import[ \t\r\n]+\"(DPI|DPI-C)\"[ \t\r\n]+function[ \t\r\n]+ { ".*" { return TOK_WILDCARD_CONNECT; } +"|=" { SV_KEYWORD(TOK_OR_ASSIGN); } +"&=" { SV_KEYWORD(TOK_AND_ASSIGN); } +"+=" { SV_KEYWORD(TOK_PLUS_ASSIGN); } +"-=" { SV_KEYWORD(TOK_SUB_ASSIGN); } +"^=" { SV_KEYWORD(TOK_XOR_ASSIGN); } + [-+]?[=*]> { if (!specify_mode) REJECT; yylval->string = new std::string(yytext); |