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| author | whitequark <whitequark@whitequark.org> | 2021-07-16 10:34:30 +0000 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2021-07-16 10:34:30 +0000 |
| commit | 37f5ed94396bd0d7161e83105e508590798f1d54 (patch) | |
| tree | 7313b9b01c13243a65ff6af228396a0f6ccc5f38 /frontends/verilog | |
| parent | 10c3214e566d8c763a68b7b18317171b707caca4 (diff) | |
| parent | b28ca7f5accccae869aab1852c5b680147b3614b (diff) | |
| download | yosys-37f5ed94396bd0d7161e83105e508590798f1d54.tar.gz yosys-37f5ed94396bd0d7161e83105e508590798f1d54.tar.bz2 yosys-37f5ed94396bd0d7161e83105e508590798f1d54.zip | |
Merge pull request #2872 from whitequark/cxxrtl-fix-2521
cxxrtl: don't expect user cell inputs to be wires
Diffstat (limited to 'frontends/verilog')
0 files changed, 0 insertions, 0 deletions